Bulusu Anand

19 papers Misc 3Journal 6Unranked 10
YearRankTypeTitle / Venue / Authors
2022 J jnl
A Variation Aware Jitter Estimation Methodology in ROs Considering Over/Undershoots in NTV Regime.
IEEE Trans. Circuits Syst. II Express Briefs
Lalit Mohan Dani, Neeraj Mishra, Bulusu Anand
2021 Misc conf
Gain Stabilization Methodology for FinFET Amplifiers Considering Self-Heating Effect.
VLSID
Shashank Banchhor, Nitanshu Chauhan, Aditya Doneria, Bulusu Anand
2019 Misc conf
MOS Varactor RO Architectures in Near Threshold Regime Using Forward Body Biasing Techniques.
VLSID
Lalit Dani, Neeraj Mishra, Bulusu Anand
2016 J jnl
A variation aware timing model for a 2-input NAND gate and its use in sub-65 nm CMOS standard cell characterization.
Microelectron. J.
Baljit Kaur, Arvind Kumar Sharma, Naushad Alam, S. K. Manhas, Bulusu Anand
2016 — conf
An efficient methodology to characterize the TSPC flip flop setup time for static timing analysis.
SMACD
Sayyaparaju Sagar Varma, Arvind Kumar Sharma, Bulusu Anand
2015 — conf
Efficient static D-latch standard cell characterization using a novel setup time model.
ISQED
Arvind Kumar Sharma, Yogendra Sharma, Sudeb Dasgupta, Bulusu Anand
2015 — conf
Timing model for two stage buffer and its application in ECSM characterization.
VDAT
Yogesh Chaurasiya, Surabhi Bhargava, Arvind Kumar Sharma, Baljit Kaur, Bulusu Anand
2015 Misc conf
Tutorial T6: FinFET Device Circuit Co-design: Issues and Challenges.
VLSID
Sudeb Dasgupta, Bulusu Anand
2014 J jnl
An Analytical Delay Model for Mechanical Stress Induced Systematic Variability Analysis in Nanoscale Circuit Design.
IEEE Trans. Circuits Syst. I Regul. Pap.
Naushad Alam, Bulusu Anand, Sudeb Dasgupta
2014 — conf
An empirical delta delay model for highly scaled CMOS inverter considering Well Proximity Effect.
VDAT
Bijay Kumar Dalai, N. Karnnan, Arvind Kumar Sharma, Bulusu Anand
2014 J jnl
Efficient ECSM Characterization Considering Voltage, Temperature, and Mechanical Stress Variability.
IEEE Trans. Circuits Syst. I Regul. Pap.
Baljit Kaur, Naushad Alam, S. K. Manhas, Bulusu Anand
2013 — conf
An efficient method for ECSM characterization of CMOS inverter in nanometer range technologies.
ISQED
Baljit Kaur, Sandeep Miryala, S. K. Manhas, Bulusu Anand
2013 J jnl
The impact of process-induced mechanical stress in narrow width devices and variable-taper CMOS buffer design.
Microelectron. Reliab.
Naushad Alam, Bulusu Anand, Sudeb Dasgupta
2013 J jnl
The impact of process-induced mechanical stress on CMOS buffer design using multi-fingered devices.
Microelectron. Reliab.
Naushad Alam, Bulusu Anand, Sudeb Dasgupta
2012 — conf
An accurate current source model for CMOS based combinational logic cell.
ISQED
Baljit Kaur, Sandeep Vundavalli, S. K. Manhas, Sudeb Dasgupta, Bulusu Anand
2012 — conf
Impact of Dummy Poly on the Process-Induced Mechanical Stress Enhanced Circuit Performance.
VDAT
Naushad Alam, Bulusu Anand, Sudeb Dasgupta
2012 — conf
Process induced mechanical stress aware poly-pitch optimization for enhanced circuit performance.
ISQED
Naushad Alam, Bulusu Anand, Sudeb Dasgupta
2012 — conf
The Impact of Process-Induced Mechanical Stress in Narrow Width Devices and Circuit Design Issues.
ISED
Naushad Alam, Bulusu Anand, Sudeb Dasgupta
2011 — conf
Efficient nanoscale VLSI standard cell library characterization using a novel delay model.
ISQED
Sandeep Miryala, Baljit Kaur, Bulusu Anand, Sanjeev Manhas