Bulent I. Dervisoglu

20 papers A* 3A 6Misc 1Journal 8Unranked 1
YearRankTypeTitle / Venue / Authors
2002 Misc conf
Reducing Time to Volume and Time to Market: Is Silicon Debug and Diagnosis the Answer?
VTS
Fidel Muradali, Mike Ricchetti, Bart Vermeulen, Bulent I. Dervisoglu, Bob Gottlieb, Bernd Koenemann, C. J. Clark
2001 A* conf
A Unified DFT Architecture for Use with IEEE 1149.1 and VSIA/IEEE P1500 Compliant Test Access Controllers.
DAC
Bulent I. Dervisoglu
1999 A conf
Design for testability: it is time to deliver it for Time-to-Market.
ITC
Bulent I. Dervisoglu
1998 A conf
Shared I/O-cell structures: a framework for extending the IEEE 1149.1 boundary-scan standard.
ITC
Bulent I. Dervisoglu, Mike Ricchetti, William Eklow
1995 J jnl
Special Report: Shared-I/O Scan Test.
IEEE Des. Test Comput.
Bulent I. Dervisoglu
1994 A* conf
Microprocessor Testing: Which Technique is Best? (Panel).
DAC
Jacob A. Abraham, Sandip Kundu, Janak H. Patel, Manuel A. d'Abreu, Bulent I. Dervisoglu, Marc E. Levitt, Hector R. Sucar, Ron G. Walther
1992 J jnl
Boundary-Scan Update: IEEE P1149.2 Description and Status Report.
IEEE Des. Test Comput.
Bulent I. Dervisoglu
1991 — conf
Application of Scan-Based DFT Methodology for Detecting Static and Timing Failures in VLSI Components.
VLSI
Bulent I. Dervisoglu, Gayvin E. Stong
1991 A conf
Design for Testability: Using Scanpath Techniques for Path-Delay Test and Measurement.
ITC
Bulent I. Dervisoglu, Gayvin E. Stong
1991 J jnl
Features of a Scan and Clock Resource chip for providing access to board-level test functions.
J. Electron. Test.
Bulent I. Dervisoglu
1990 J jnl
Application of scan hardware and software for debug and diagnostics in a workstation environment.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Bulent I. Dervisoglu
1990 A conf
Towards a standard approach for controlling board-level test functions.
ITC
Bulent I. Dervisoglu
1989 A* conf
ATLAS/ELA: Scan-based Software Tools for Reducing System Debug Time in a State-of-the-art Workstation.
DAC
Bulent I. Dervisoglu, M. A. Keil
1989 J jnl
Scan-path architecture for pseudorandom testing.
IEEE Des. Test
Bulent I. Dervisoglu
1988 A conf
Using Scan Technology for Debug and Diagnostics in a Workstation Environment.
ITC
Bulent I. Dervisoglu
1984 A conf
On Coosing a Hardware Descriptive Language for Digital Systems Testing/Verification.
ITC
Bulent I. Dervisoglu
1981 J jnl
A Hard Progammable Control Unit Design Using VLSI Technology.
IEEE Trans. Computers
Bulent I. Dervisoglu, Donald J. Criscione
1980 J jnl
Theory and Design of Mixed-Mode Sequential Machines.
IEEE Trans. Computers
Bulent I. Dervisoglu, Howard A. Sholl
1974 J jnl
Hardware description languages in Great Britain.
Computer
Bulent I. Dervisoglu
1973 — —
Computer aided design techniques applied to logic design.
Bulent I. Dervisoglu