Brucek Khailany

115 papers A* 27A 14B 2C 2Journal 49Unranked 21

Year	Rank	Type	Title / Venue / Authors
2026	—	`conf`	31.9 Alpha-Vision: A Real-Time Always-on Vision Processor with 787µs Face Detection Latency in <5mW. ISSCC Ben Keller, Rangharajan Venkatesan, Steve Dai, Jason Clemons, Matthew Fojtik, Muya Chang, Thierry Tambe, Nathaniel Ross Pinckney, Stephen G. Tell, Qijing Huang, Shalini De Mello, Brucek Khailany
2026	J	`jnl`	GRPO with State Mutations: Improving LLM-Based Hardware Test Plan Generation. CoRR Dimple Vijay Kochar, Nathaniel Ross Pinckney, Guan-Ting Liu, Chia-Tung Ho, Chenhui Deng, Haoxing Ren, Brucek Khailany
2026	J	`jnl`	GaloisSAT: Differentiable Boolean Satisfiability Solving via Finite Field Algebra. CoRR Curie Kim, Carsten Portner, Mingju Liu, Steve Dai, Haoxing Ren, Brucek Khailany, Alvaro Velasquez, Ismail Alkhouri, Cunxi Yu
2026	J	`jnl`	LLM4Cov: Execution-Aware Agentic Learning for High-coverage Testbench Generation. CoRR Hejia Zhang, Zhongming Yu, Chia-Tung Ho, Haoxing Ren, Brucek Khailany, Jishen Zhao
2026	J	`jnl`	QuRL: Efficient Reinforcement Learning with Quantized Rollout. CoRR Yuhang Li, Reena Elangovan, Xin Dong, Priyadarshini Panda, Brucek Khailany
2025	A	`conf`	Augmenting Simulated Noisy Quantum Data Collection by Orders of Magnitude Using Pre-Trajectory Sampling with Batched Execution. SC Taylor Lee Patti, Thien Nguyen, Justin Gage Lietz, Alex McCaskey, Brucek Khailany
2025	J	`jnl`	BCQ: Block Clustered Quantization for 4-bit (W4A4) LLM Inference. CoRR Reena Elangovan, Charbel Sakr, Anand Raghunathan, Brucek Khailany
2025	J	`jnl`	Comprehensive Verilog Design Problems: A Next-Generation Benchmark Dataset for Evaluating Large Language Models and Agents on RTL Design and Verification. CoRR Nathaniel Ross Pinckney, Chenhui Deng, Chia-Tung Ho, Yun-Da Tsai, Mingjie Liu, Wenfei Zhou, Brucek Khailany, Haoxing Ren
2025	J	`jnl`	FGMP: Fine-Grained Mixed-Precision Weight and Activation Quantization for Hardware-Accelerated LLM Inference. CoRR Coleman Hooper, Charbel Sakr, Ben Keller, Rangharajan Venkatesan, Kurt Keutzer, Yakun Sophia Shao, Brucek Khailany
2025	J	`jnl`	GPU-accelerated Effective Hamiltonian Calculator. Quantum Abhishek Chakraborty, Taylor L. Patti, Brucek Khailany, Andrew N. Jordan, Anima Anandkumar
2025	J	`jnl`	GalaxyDiT: Efficient Video Generation with Guidance Alignment and Adaptive Proxy in Diffusion Transformers. CoRR Zhiye Song, Steve Dai, Ben Keller, Brucek Khailany
2025	A*	`conf`	GauRast: Enhancing GPU Triangle Rasterizers to Accelerate 3D Gaussian Splatting. DAC Sixu Li, Ben Keller, Yingyan Celine Lin, Brucek Khailany
2025	J	`jnl`	GauRast: Enhancing GPU Triangle Rasterizers to Accelerate 3D Gaussian Splatting. CoRR Sixu Li, Ben Keller, Yingyan Celine Lin, Brucek Khailany
2025	J	`jnl`	LO-BCQ: Locally Optimal Block Clustered Quantization for 4-bit (W4A4) LLM Inference. Trans. Mach. Learn. Res. Reena Elangovan, Charbel Sakr, Anand Raghunathan, Brucek Khailany
2025	J	`jnl`	Marco: Configurable Graph-Based Task Solving and Multi-AI Agents Framework for Hardware Design. CoRR Chia-Tung Ho, Jing Gong, Yunsheng Bai, Chenhui Deng, Haoxing Ren, Brucek Khailany
2025	J	`jnl`	Revisiting VerilogEval: A Year of Improvements in Large-Language Models for Hardware Code Generation. ACM Trans. Design Autom. Electr. Syst. Nathaniel Ross Pinckney, Christopher Batten, Mingjie Liu, Haoxing Ren, Brucek Khailany
2025	A*	`conf`	SQ-DM: Accelerating Diffusion Models with Aggressive Quantization and Temporal Sparsity. DAC Zichen Fan, Steve Dai, Rangharajan Venkatesan, Dennis Sylvester, Brucek Khailany
2025	J	`jnl`	SQ-DM: Accelerating Diffusion Models with Aggressive Quantization and Temporal Sparsity. CoRR Zichen Fan, Steve Dai, Rangharajan Venkatesan, Dennis Sylvester, Brucek Khailany
2025	J	`jnl`	ThinKV: Thought-Adaptive KV Cache Compression for Efficient Reasoning Models. CoRR Akshat Ramachandran, Marina Neseem, Charbel Sakr, Rangharajan Venkatesan, Brucek Khailany, Tushar Krishna
2025	J	`jnl`	TurboSAT: Gradient-Guided Boolean Satisfiability Accelerated on GPU-CPU Hybrid System. CoRR Steve Dai, Cunxi Yu, Kalyan Krishnamani, Brucek Khailany
2025	A*	`conf`	VerilogCoder: Autonomous Verilog Coding Agents with Graph-based Planning and Abstract Syntax Tree (AST)-based Waveform Tracing Tool. AAAI Chia-Tung Ho, Haoxing Ren, Brucek Khailany
2024	A*	`conf`	ESPACE: Dimensionality Reduction of Activations for Model Compression. NeurIPS Charbel Sakr, Brucek Khailany
2024	J	`jnl`	ESPACE: Dimensionality Reduction of Activations for Model Compression. CoRR Charbel Sakr, Brucek Khailany
2024	A	`conf`	GL0AM: GPU Logic Simulation Using 0-Delay and Re-simulation Acceleration Method. ICCAD Yanqing Zhang, Haoxing Ren, Brucek Khailany
2024	—	`conf`	PyHDL-Eval: An LLM Evaluation Framework for Hardware Design Using Python-Embedded DSLs. MLCAD Christopher Batten, Nathaniel Ross Pinckney, Mingjie Liu, Haoxing Ren, Brucek Khailany
2024	J	`jnl`	Revisiting VerilogEval: Newer LLMs, In-Context Learning, and Specification-to-RTL Tasks. CoRR Nathaniel Ross Pinckney, Christopher Batten, Mingjie Liu, Haoxing Ren, Brucek Khailany
2024	J	`jnl`	VerilogCoder: Autonomous Verilog Coding Agents with Graph-based Planning and Abstract Syntax Tree (AST)-based Waveform Tracing Tool. CoRR Chia-Tung Ho, Haoxing Ren, Brucek Khailany
2023	J	`jnl`	A 95.6-TOPS/W Deep Learning Inference Accelerator With Per-Vector Scaled 4-bit Quantization in 5 nm. IEEE J. Solid State Circuits Ben Keller, Rangharajan Venkatesan, Steve Dai, Stephen G. Tell, Brian Zimmer, Charbel Sakr, William J. Dally, C. Thomas Gray, Brucek Khailany
2023	A	`conf`	An Adversarial Active Sampling-Based Data Augmentation Framework for AI-Assisted Lithography Modeling. ICCAD Mingjie Liu, Haoyu Yang, Brucek Khailany, Haoxing Ren
2023	—	`conf`	AutoDMP: Automated DREAMPlace-based Macro Placement. ISPD Anthony Agnesina, Puranjay Rajvanshi, Tian Yang, Geraldo Pradipta, Austin Jiao, Ben Keller, Brucek Khailany, Haoxing Ren
2023	J	`jnl`	ChipNeMo: Domain-Adapted LLMs for Chip Design. CoRR Mingjie Liu, Teodor-Dumitru Ene, Robert Kirby, Chris Cheng, Nathaniel Ross Pinckney, Rongjian Liang, Jonah Alben, Himyanshu Anand, Sanmitra Banerjee, Ismet Bayraktaroglu, Bonita Bhaskaran, Bryan Catanzaro, Arjun Chaudhuri, Sharon Clay, Bill Dally, Laura Dang, Parikshit Deshpande, Siddhanth Dhodhi, Sameer Halepete, Eric Hill, Jiashang Hu, Sumit Jain, Brucek Khailany, Kishor Kunal, Xiaowei Li, Hao Liu, Stuart F. Oberman, Sujeet Omar, Sreedhar Pratty, Jonathan Raiman, Ambar Sarkar, Zhengjiang Shao, Hanfei Sun, Pratik P. Suthar, Varun Tej, Kaizhe Xu, Haoxing Ren
2023	A*	`conf`	Efficient Transformer Inference with Statically Structured Sparse Attention. DAC Steve Dai, Hasan Genc, Rangharajan Venkatesan, Brucek Khailany
2023	A*	`conf`	GenFuzz: GPU-accelerated Hardware Fuzzing using Genetic Algorithm with Multiple Inputs. DAC Dian-Lun Lin, Yanqing Zhang, Haoxing Ren, Brucek Khailany, Shih-Hsin Wang, Tsung-Wei Huang
2023	A	`conf`	Invited Paper: VerilogEval: Evaluating Large Language Models for Verilog Code Generation. ICCAD Mingjie Liu, Nathaniel Ross Pinckney, Brucek Khailany, Haoxing Ren
2023	A*	`conf`	Late Breaking Results: Test Selection For RTL Coverage By Unsupervised Learning From Fast Functional Simulation. DAC Rongjian Liang, Nathaniel Ross Pinckney, Yuji Chai, Haoxin Ren, Brucek Khailany
2023	J	`jnl`	Machine Learning and Algorithms: Let Us Team Up for EDA. IEEE Des. Test Haoxing Ren, Brucek Khailany, Matthew Fojtik, Yanqing Zhang
2023	—	`conf`	NVCell 2: Routability-Driven Standard Cell Layout in Advanced Nodes with Lattice Graph Routability Model. ISPD Chia-Tung Ho, Alvin Ho, Matthew Fojtik, Minsoo Kim, Shang Wei, Yaguang Li, Brucek Khailany, Haoxing Ren
2023	J	`jnl`	VerilogEval: Evaluating Large Language Models for Verilog Code Generation. CoRR Mingjie Liu, Nathaniel Ross Pinckney, Brucek Khailany, Haoxing Ren
2022	—	`conf`	A 17-95.6 TOPS/W Deep Learning Inference Accelerator with Per-Vector Scaled 4-bit Quantization for Transformers in 5nm. VLSI Technology and Circuits Ben Keller, Rangharajan Venkatesan, Steve Dai, Stephen G. Tell, Brian Zimmer, William J. Dally, C. Thomas Gray, Brucek Khailany
2022	J	`jnl`	An Adversarial Active Sampling-based Data Augmentation Framework for Manufacturable Chip Design. CoRR Mingjie Liu, Haoyu Yang, Zongyi Li, Kumara Sastry, Saumyadip Mukhopadhyay, Selim Dogru, Anima Anandkumar, David Z. Pan, Brucek Khailany, Haoxing Ren
2022	—	`conf`	AutoCRAFT: Layout Automation for Custom Circuits in Advanced FinFET Technologies. ISPD Hao Chen, Walker J. Turner, Sanquan Song, Keren Zhu, George F. Kokai, Brian Zimmer, C. Thomas Gray, Brucek Khailany, David Z. Pan, Haoxing Ren
2022	B	`conf`	From RTL to CUDA: A GPU Acceleration Flow for RTL Simulation with Batch Stimulus. ICPP Dian-Lun Lin, Haoxing Ren, Yanqing Zhang, Brucek Khailany, Tsung-Wei Huang
2022	J	`jnl`	GATSPI: GPU Accelerated Gate-Level Simulation for Power Improvement. CoRR Yanqing Zhang, Haoxing Ren, Akshay Sridharan, Brucek Khailany
2022	A*	`conf`	GATSPI: GPU accelerated gate-level simulation for power improvement. DAC Yanqing Zhang, Haoxing Ren, Akshay Sridharan, Brucek Khailany
2022	A*	`conf`	Generative self-supervised learning for gate sizing: invited. DAC Siddhartha Nath, Geraldo Pradipta, Corey Hu, Tian Yang, Brucek Khailany, Haoxing Ren
2022	J	`jnl`	Generic Lithography Modeling with Dual-band Optics-Inspired Neural Networks. CoRR Haoyu Yang, Zongyi Li, Kumara Sastry, Saumyadip Mukhopadhyay, Mark Kilgard, Anima Anandkumar, Brucek Khailany, Vivek Singh, Haoxing Ren
2022	A*	`conf`	Generic lithography modeling with dual-band optics-inspired neural networks. DAC Haoyu Yang, Zongyi Li, Kumara Sastry, Saumyadip Mukhopadhyay, Mark Kilgard, Anima Anandkumar, Brucek Khailany, Vivek Singh, Haoxing Ren
2022	J	`jnl`	HEAT: Hardware-Efficient Automatic Tensor Decomposition for Transformer Compression. CoRR Jiaqi Gu, Ben Keller, Jean Kossaifi, Anima Anandkumar, Brucek Khailany, David Z. Pan
2022	J	`jnl`	LNS-Madam: Low-Precision Training in Logarithmic Number System Using Multiplicative Weight Update. IEEE Trans. Computers Jiawei Zhao, Steve Dai, Rangharajan Venkatesan, Brian Zimmer, Mustafa Fayez Ali, Ming-Yu Liu, Brucek Khailany, William J. Dally, Anima Anandkumar
2022	J	`jnl`	Large Scale Mask Optimization Via Convolutional Fourier Neural Operator and Litho-Guided Self Training. CoRR Haoyu Yang, Zongyi Li, Kumara Sastry, Saumyadip Mukhopadhyay, Anima Anandkumar, Brucek Khailany, Vivek Singh, Haoxing Ren
2022	A*	`conf`	Optimal Clipping and Magnitude-aware Differentiation for Improved Quantization-aware Training. ICML Charbel Sakr, Steve Dai, Rangharajan Venkatesan, Brian Zimmer, William J. Dally, Brucek Khailany
2022	J	`jnl`	Optimal Clipping and Magnitude-aware Differentiation for Improved Quantization-aware Training. CoRR Charbel Sakr, Steve Dai, Rangharajan Venkatesan, Brian Zimmer, William J. Dally, Brucek Khailany
2022	A	`conf`	TransSizer: A Novel Transformer-Based Fast Gate Sizer. ICCAD Siddhartha Nath, Geraldo Pradipta, Corey Hu, Tian Yang, Brucek Khailany, Haoxing Ren
2022	—	`conf`	XT-PRAGGMA: Crosstalk Pessimism Reduction Achieved with GPU Gate-level Simulations and Machine Learning. MLCAD Vidya A. Chhabria, Ben Keller, Yanqing Zhang, Sandeep Vollala, Sreedhar Pratty, Haoxing Ren, Brucek Khailany
2021	A	`conf`	2021 ICCAD CAD Contest Problem C: GPU Accelerated Logic Rewriting. ICCAD Ghasem Pasandi, Sreedhar Pratty, David Brown, Yanqing Zhang, Haoxing Ren, Brucek Khailany
2021	—	`conf`	3.2 The A100 Datacenter GPU and Ampere Architecture. ISSCC Jack Choquette, Ming-Ju Edward Lee, Ronny Krashinsky, Vishnu Balan, Brucek Khailany
2021	J	`jnl`	DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yibo Lin, Zixuan Jiang, Jiaqi Gu, Wuxi Li, Shounak Dhar, Haoxing Ren, Brucek Khailany, David Z. Pan
2021	A	`conf`	IPA: Floorplan-Aware SystemC Interconnect Performance Modeling and Generation for HLS-based SoCs. ICCAD Nathaniel Ross Pinckney, Rangharajan Venkatesan, Ben Keller, Brucek Khailany
2021	J	`jnl`	Low-Precision Training in Logarithmic Number System using Multiplicative Weight Update. CoRR Jiawei Zhao, Steve Dai, Rangharajan Venkatesan, Ming-Yu Liu, Brucek Khailany, Bill Dally, Anima Anandkumar
2021	A	`conf`	MAVIREC: ML-Aided Vectored IR-Drop Estimation and Classification. DATE Vidya A. Chhabria, Yanqing Zhang, Haoxing Ren, Ben Keller, Brucek Khailany, Sachin S. Sapatnekar
2021	J	`jnl`	NVCell: Standard Cell Layout in Advanced Technology Nodes with Reinforcement Learning. CoRR Haoxing Ren, Matthew Fojtik, Brucek Khailany
2021	A	`conf`	Optimizing VLSI Implementation with Reinforcement Learning - ICCAD Special Session Paper. ICCAD Haoxing Ren, Saad Godil, Brucek Khailany, Robert Kirby, Haiguang Liao, Siddhartha Nath, Jonathan Raiman, Rajarshi Roy
2021	A	`conf`	Parasitic-Aware Analog Circuit Sizing with Graph Neural Networks and Bayesian Optimization. DATE Mingjie Liu, Walker J. Turner, George F. Kokai, Brucek Khailany, David Z. Pan, Haoxing Ren
2021	J	`jnl`	Simba: scaling deep-learning inference with chiplet-based architecture. Commun. ACM Yakun Sophia Shao, Jason Clemons, Rangharajan Venkatesan, Brian Zimmer, Matthew Fojtik, Nan Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Ross Pinckney, Priyanka Raina, Stephen G. Tell, Yanqing Zhang, William J. Dally, Joel S. Emer, C. Thomas Gray, Brucek Khailany, Stephen W. Keckler
2021	A*	`conf`	Softermax: Hardware/Software Co-Design of an Efficient Softmax for Transformers. DAC Jacob R. Stevens, Rangharajan Venkatesan, Steve Dai, Brucek Khailany, Anand Raghunathan
2021	J	`jnl`	Softermax: Hardware/Software Co-Design of an Efficient Softmax for Transformers. CoRR Jacob R. Stevens, Rangharajan Venkatesan, Steve Dai, Brucek Khailany, Anand Raghunathan
2021	—	`conf`	VS-Quant: Per-vector Scaled Quantization for Accurate Low-Precision Neural Network Inference. MLSys Steve Dai, Rangharajan Venkatesan, Mark Ren, Brian Zimmer, William J. Dally, Brucek Khailany
2021	J	`jnl`	VS-Quant: Per-vector Scaled Quantization for Accurate Low-Precision Neural Network Inference. CoRR Steve Dai, Rangharajan Venkatesan, Haoxing Ren, Brian Zimmer, William J. Dally, Brucek Khailany
2021	J	`jnl`	Verifying High-Level Latency-Insensitive Designs with Formal Model Checking. CoRR Steve Dai, Alicia Klinefelter, Haoxing Ren, Rangharajan Venkatesan, Ben Keller, Nathaniel Ross Pinckney, Brucek Khailany
2020	J	`jnl`	A 0.32-128 TOPS, Scalable Multi-Chip-Module-Based Deep Neural Network Inference Accelerator With Ground-Referenced Signaling in 16 nm. IEEE J. Solid State Circuits Brian Zimmer, Rangharajan Venkatesan, Yakun Sophia Shao, Jason Clemons, Matthew Fojtik, Nan Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Ross Pinckney, Priyanka Raina, Stephen G. Tell, Yanqing Zhang, William J. Dally, Joel S. Emer, C. Thomas Gray, Stephen W. Keckler, Brucek Khailany
2020	J	`jnl`	ABCDPlace: Accelerated Batch-Based Concurrent Detailed Placement on Multithreaded CPUs and GPUs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yibo Lin, Wuxi Li, Jiaqi Gu, Haoxing Ren, Brucek Khailany, David Z. Pan
2020	J	`jnl`	Accelerating Chip Design With Machine Learning. IEEE Micro Brucek Khailany, Haoxing Ren, Steve Dai, Saad Godil, Ben Keller, Robert Kirby, Alicia Klinefelter, Rangharajan Venkatesan, Yanqing Zhang, Bryan Catanzaro, William J. Dally
2020	—	`conf`	Accelerating Chip Design with Machine Learning. MLCAD Brucek Khailany
2020	—	`conf`	FIST: A Feature-Importance Sampling and Tree-Based Method for Automatic Design Flow Parameter Tuning. ASP-DAC Zhiyao Xie, Guan-Qi Fang, Yu-Hung Huang, Haoxing Ren, Yanqing Zhang, Brucek Khailany, Shao-Yun Fang, Jiang Hu, Yiran Chen, Erick Carvajal Barboza
2020	J	`jnl`	FIST: A Feature-Importance Sampling and Tree-Based Method for Automatic Design Flow Parameter Tuning. CoRR Zhiyao Xie, Guan-Qi Fang, Yu-Hung Huang, Haoxing Ren, Yanqing Zhang, Brucek Khailany, Shao-Yun Fang, Jiang Hu, Yiran Chen, Erick Carvajal Barboza
2020	A*	`conf`	GRANNITE: Graph Neural Network Inference for Transferable Power Estimation. DAC Yanqing Zhang, Haoxing Ren, Brucek Khailany
2020	J	`jnl`	MAVIREC: ML-Aided Vectored IR-DropEstimation and Classification. CoRR Vidya A. Chhabria, Yanqing Zhang, Haoxing Ren, Ben Keller, Brucek Khailany, Sachin S. Sapatnekar
2020	A	`conf`	Opportunities for RTL and Gate Level Simulation using GPUs (Invited Talk). ICCAD Yanqing Zhang, Haoxing Ren, Brucek Khailany
2020	—	`conf`	PowerNet: Transferable Dynamic IR Drop Estimation via Maximum Convolutional Neural Network. ASP-DAC Zhiyao Xie, Haoxing Ren, Brucek Khailany, Ye Sheng, Santosh Santosh, Jiang Hu, Yiran Chen
2020	J	`jnl`	PowerNet: Transferable Dynamic IR Drop Estimation via Maximum Convolutional Neural Network. CoRR Zhiyao Xie, Haoxing Ren, Brucek Khailany, Ye Sheng, Santosh Santosh, Jiang Hu, Yiran Chen
2020	A	`conf`	Problem C: GPU Accelerated Logic Re-simulation : (Invited Talk). ICCAD Yanqing Zhang, Haoxing Ren, Ben Keller, Brucek Khailany
2019	—	`conf`	A 0.11 PJ/OP, 0.32-128 Tops, Scalable Multi-Chip-Module-Based Deep Neural Network Accelerator Designed with A High-Productivity vlsi Methodology. Hot Chips Symposium Rangharajan Venkatesan, Yakun Sophia Shao, Brian Zimmer, Jason Clemons, Matthew Fojtik, Nan Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Ross Pinckney, Priyanka Raina, Stephen G. Tell, Yanqing Zhang, William J. Dally, Joel S. Emer, C. Thomas Gray, Stephen W. Keckler, Brucek Khailany
2019	—	`conf`	A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator with Ground-Reference Signaling in 16nm. VLSI Circuits Brian Zimmer, Rangharajan Venkatesan, Yakun Sophia Shao, Jason Clemons, Matthew Fojtik, Nan Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Ross Pinckney, Priyanka Raina, Stephen G. Tell, Yanqing Zhang, William J. Dally, Joel S. Emer, C. Thomas Gray, Stephen W. Keckler, Brucek Khailany
2019	—	`conf`	A Fine-Grained GALS SoC with Pausible Adaptive Clocking in 16 nm FinFET. ASYNC Matthew Fojtik, Ben Keller, Alicia Klinefelter, Nathaniel Ross Pinckney, Stephen G. Tell, Brian Zimmer, Tezaswi Raja, Kevin Zhou, William J. Dally, Brucek Khailany
2019	A*	`conf`	Analog/Mixed-Signal Hardware Error Modeling for Deep Learning Inference. DAC Angad S. Rekhi, Brian Zimmer, Nikola Nedovic, Ningxi Liu, Rangharajan Venkatesan, Miaorong Wang, Brucek Khailany, William J. Dally, C. Thomas Gray
2019	A*	`conf`	DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement. DAC Yibo Lin, Shounak Dhar, Wuxi Li, Haoxing Ren, Brucek Khailany, David Z. Pan
2019	A*	`conf`	High Performance Graph Convolutional Networks with Applications in Testability Analysis. DAC Yuzhe Ma, Haoxing Ren, Brucek Khailany, Harbinder Sikka, Lijuan Luo, Karthikeyan Natarajan, Bei Yu
2019	A	`conf`	MAGNet: A Modular Accelerator Generator for Neural Networks. ICCAD Rangharajan Venkatesan, Yakun Sophia Shao, Miaorong Wang, Jason Clemons, Steve Dai, Matthew Fojtik, Ben Keller, Alicia Klinefelter, Nathaniel Ross Pinckney, Priyanka Raina, Yanqing Zhang, Brian Zimmer, William J. Dally, Joel S. Emer, Stephen W. Keckler, Brucek Khailany
2019	A*	`conf`	PRIMAL: Power Inference using Machine Learning. DAC Yuan Zhou, Haoxing Ren, Yanqing Zhang, Ben Keller, Brucek Khailany, Zhiru Zhang
2019	A*	`conf`	Simba: Scaling Deep-Learning Inference with Multi-Chip-Module-Based Architecture. MICRO Yakun Sophia Shao, Jason Clemons, Rangharajan Venkatesan, Brian Zimmer, Matthew Fojtik, Nan Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Ross Pinckney, Priyanka Raina, Stephen G. Tell, Yanqing Zhang, William J. Dally, Joel S. Emer, C. Thomas Gray, Brucek Khailany, Stephen W. Keckler
2019	B	`conf`	Timeloop: A Systematic Approach to DNN Accelerator Evaluation. ISPASS Angshuman Parashar, Priyanka Raina, Yakun Sophia Shao, Yu-Hsin Chen, Victor A. Ying, Anurag Mukkara, Rangharajan Venkatesan, Brucek Khailany, Stephen W. Keckler, Joel S. Emer
2018	A*	`conf`	A modular digital VLSI flow for high-productivity SoC design. DAC Brucek Khailany, Evgeni Khmer, Rangharajan Venkatesan, Jason Clemons, Joel S. Emer, Matthew Fojtik, Alicia Klinefelter, Michael Pellauer, Nathaniel Ross Pinckney, Yakun Sophia Shao, Shreesha Srinath, Christopher Torng, Sam Likun Xi, Yanqing Zhang, Brian Zimmer
2018	—	`conf`	Hardware-Enabled Artificial Intelligence. VLSI Circuits William J. Dally, C. Thomas Gray, John Poulton, Brucek Khailany, John M. Wilson, Larry R. Dennison
2017	A*	`conf`	SCNN: An Accelerator for Compressed-sparse Convolutional Neural Networks. ISCA Angshuman Parashar, Minsoo Rhu, Anurag Mukkara, Antonio Puglielli, Rangharajan Venkatesan, Brucek Khailany, Joel S. Emer, Stephen W. Keckler, William J. Dally
2017	J	`jnl`	SCNN: An Accelerator for Compressed-sparse Convolutional Neural Networks. CoRR Angshuman Parashar, Minsoo Rhu, Anurag Mukkara, Antonio Puglielli, Rangharajan Venkatesan, Brucek Khailany, Joel S. Emer, Stephen W. Keckler, William J. Dally
2016	A*	`conf`	A real-time energy-efficient superpixel hardware accelerator for mobile computer vision applications. DAC Injoon Hong, Jason Clemons, Rangharajan Venkatesan, Iuri Frosio, Brucek Khailany, Stephen W. Keckler
2016	—	`conf`	Modeling and Analysis of Power Supply Noise Tolerance with Fine-Grained GALS Adaptive Clocks. ASYNC Divya Akella Kamakshi, Matthew Fojtik, Brucek Khailany, Sudhir S. Kudva, Yaping Zhou, Benton H. Calhoun
2015	—	`conf`	A Pausible Bisynchronous FIFO for GALS Systems. ASYNC Ben Keller, Matthew Fojtik, Brucek Khailany
2013	—	`conf`	GPU design in a power-limited era. MSE Brucek Khailany
2012	A*	`conf`	Unifying Primary Cache, Scratch, and Register File Memories in a Throughput Processor. MICRO Mark Gebhart, Stephen W. Keckler, Brucek Khailany, Ronny Krashinsky, William J. Dally
2011	A	`conf`	CudaDMA: optimizing GPU memory bandwidth via warp specialization. SC Michael Bauer, Henry Cook, Brucek Khailany
2011	J	`jnl`	GPUs and the Future of Parallel Computing. IEEE Micro Stephen W. Keckler, William J. Dally, Brucek Khailany, Michael Garland, David Glasco
2008	J	`jnl`	A Programmable 512 GOPS Stream Processor for Signal, Image, and Video Processing. IEEE J. Solid State Circuits Brucek Khailany, Ted Williams, Jim Lin, Eileen Peters Long, Mark Rygh, DeForest Tovey, William J. Dally
2007	—	`conf`	A Programmable 512 GOPS Stream Processor for Signal, Image, and Video Processing. ISSCC Brucek Khailany, Ted Williams, Jim Lin, Eileen Long, Mark Rygh, DeForest Tovey, William J. Dally
2004	A*	`conf`	Evaluating the Imagine Stream Architecture. ISCA Jung Ho Ahn, William J. Dally, Brucek Khailany, Ujval J. Kapasi, Abhishek Das
2004	J	`jnl`	Stream Processors: Progammability and Efficiency. ACM Queue William J. Dally, Ujval J. Kapasi, Brucek Khailany, Jung Ho Ahn, Abhishek Das
2003	A*	`conf`	Exploring the VLSI Scalability of Stream Processors. HPCA Brucek Khailany, William J. Dally, Scott Rixner, Ujval J. Kapasi, John D. Owens, Brian Towles
2003	J	`jnl`	Programmable Stream Processors. Computer Ujval J. Kapasi, Scott Rixner, William J. Dally, Brucek Khailany, Jung Ho Ahn, Peter R. Mattson, John D. Owens
2002	—	`conf`	Comparing Reyes and OpenGL on a Stream Architecture. Graphics Hardware John D. Owens, Brucek Khailany, Brian Towles, William J. Dally
2002	C	`conf`	The Imagine Stream Processor. ICCD Ujval J. Kapasi, William J. Dally, Scott Rixner, John D. Owens, Brucek Khailany
2002	C	`conf`	VLSI Design and Verification of the Imagine Processor. ICCD Brucek Khailany, William J. Dally, Andrew Chang, Ujval J. Kapasi, Jinyung Namkoong, Brian Towles
2001	J	`jnl`	Imagine: Media Processing with Streams. IEEE Micro Brucek Khailany, William J. Dally, Ujval J. Kapasi, Peter R. Mattson, Jinyung Namkoong, John D. Owens, Brian Towles, Andrew Chang, Scott Rixner
2000	A*	`conf`	Efficient conditional operations for data-parallel architectures. MICRO Ujval J. Kapasi, William J. Dally, Scott Rixner, Peter R. Mattson, John D. Owens, Brucek Khailany
2000	A*	`conf`	Register Organization for Media Processing. HPCA Scott Rixner, William J. Dally, Brucek Khailany, Peter R. Mattson, Ujval J. Kapasi, John D. Owens
1998	A*	`conf`	A Bandwidth-efficient Architecture for Media Processing. MICRO Scott Rixner, William J. Dally, Ujval J. Kapasi, Brucek Khailany, Abelardo López-Lagunas, Peter R. Mattson, John D. Owens