Brion L. Keller

41 papers A 17B 1C 3Journal 7Unranked 13

Year	Rank	Type	Title / Venue / Authors
2015	J	`jnl`	A DfT Architecture and Tool Flow for 3-D SICs With Test Data Compression, Embedded Cores, and Multiple Towers. IEEE Des. Test Christos Papameletis, Brion L. Keller, Vivek Chickermane, Said Hamdioui, Erik Jan Marinissen
2015	—	`conf`	At-Speed Testing of Inter-Die Connections of 3D-SICs in the Presence of Shore Logic. ATS Konstantin Shibin, Vivek Chickermane, Brion L. Keller, Christos Papameletis, Erik Jan Marinissen
2014	A	`conf`	Efficient testing of hierarchical core-based SOCs. ITC Brion L. Keller, Krishna Chakravadhanula, Brian Foutz, Vivek Chickermane, Akhil Garg, Richard Schoonover, James Sage, Don Pearl, Thomas J. Snethen
2013	B	`conf`	Automated DfT insertion and test generation for 3D-SICs with embedded cores and multiple towers. ETS Christos Papameletis, Brion L. Keller, Vivek Chickermane, Erik Jan Marinissen, Said Hamdioui
2013	A	`conf`	Test and debug strategy for TSMC CoWoS™ stacking process based heterogeneous 3D IC: A silicon case study. ITC Sandeep Kumar Goel, Saman Adham, Min-Jer Wang, Ji-Jan Chen, Tze-Chiang Huang, Ashok Mehta, Frank Lee, Vivek Chickermane, Brion L. Keller, Thomas Valind, Subhasish Mukherjee, Navdeep Sood, Jeongho Cho, Hayden Hyungdong Lee, Jungi Choi, Sangdoo Kim
2012	A	`conf`	DfT architecture and ATPG for Interconnect tests of JEDEC Wide-I/O memory-on-logic die stacks. ITC Sergej Deutsch, Brion L. Keller, Vivek Chickermane, Subhasish Mukherjee, Navdeep Sood, Sandeep Kumar Goel, Ji-Jan Chen, Ashok Mehta, Frank Lee, Erik Jan Marinissen
2011	—	`conf`	Automation of 3D-DfT Insertion. Asian Test Symposium Sergej Deutsch, Vivek Chickermane, Brion L. Keller, Subhasish Mukherjee, Mario Konijnenburg, Erik Jan Marinissen, Sandeep Kumar Goel
2010	A	`conf`	Low cost at-speed testing using On-Product Clock Generation compatible with test compression. ITC Brion L. Keller, Krishna Chakravadhanula, Brian Foutz, Vivek Chickermane, R. Malneedi, Thomas J. Snethen, Vikram Iyengar, David E. Lackey, Gary Grise
2010	J	`jnl`	Reduction of Test Data Volume and Improvement of Diagnosability Using Hybrid Compression. IEICE Trans. Inf. Syst. Anis Uzzaman, Brion L. Keller, Brian Foutz, Sandeep Bhatia, Thomas Bartenstein, Masayuki Arai, Kazuhiko Iwasaki
2009	—	`conf`	A Partially-Exhaustive Gate Transition Fault Model. Asian Test Symposium Brion L. Keller, Dale Meehl, Anis Uzzaman, Richard Billings
2009	J	`jnl`	Automatic Handling of Programmable On-Product Clock Generation (OPCG) Circuitry for Low Power Aware Delay Test. J. Low Power Electron. Anis Uzzaman, Brion L. Keller, Thomas J. Snethen, Kazuhiko Iwasaki, Masayuki Arai
2009	J	`jnl`	CTL and Its Usage in the EDA Industry. IEEE Des. Test Comput. Rohit Kapur, Paul Reuter, Sandeep Bhatia, Brion L. Keller
2009	A	`conf`	Capture power reduction using clock gating aware test generation. ITC Krishna Chakravadhanula, Vivek Chickermane, Brion L. Keller, Patrick R. Gallagher Jr., Prashant Narang
2009	—	`conf`	Why is Conventional ATPG Not Sufficient for Advanced Low Power Designs?. Asian Test Symposium Krishna Chakravadhanula, Vivek Chickermane, Brion L. Keller, Patrick R. Gallagher Jr., Anis Uzzaman
2008	—	`conf`	Optimizing Test Data Volume Using Hybrid Compression. ATS Brion L. Keller, Sandeep Bhatia, Thomas Bartenstein, Brian Foutz, Anis Uzzaman
2008	—	`conf`	Test Generation for State Retention Logic. ATS Krishna Chakravadhanula, Vivek Chickermane, Brion L. Keller, Patrick R. Gallagher Jr., Steven Gregor
2007	—	`conf`	A Review of Power Strategies for DFT and ATPG. ATS Brion L. Keller, Tom Jackson, Anis Uzzaman
2007	A	`conf`	Automated handling of programmable on-product clock generation (OPCG) circuitry for delay test vector generation. ITC Anis Uzzaman, Bibo Li, Thomas J. Snethen, Brion L. Keller, Gary Grise
2007	—	`conf`	Using Programmable On-Product Clock Generation (OPCG) for Delay Test. ATS Brion L. Keller, Anis Uzzaman, Bibo Li, Thomas J. Snethen
2006	—	`conf`	A Scalable Architecture for On-Chip Compression: Options and Trade-Offs. ATS Anis Uzzaman, Brion L. Keller, Vivek Chickermane
2006	A	`conf`	OCI: Open Compression Interface. ITC Bruce Cory, Rohit Kapur, Mick Tegethoff, Mark Kassab, Brion L. Keller, Kee Sup Kim, Dwayne Burek, Steven F. Oakland, Benoit Nadeau-Dostie
2005	A	`conf`	Encounter test OPMISR ITC Brion L. Keller
2005	—	`conf`	Low Cost Delay Testing of Nanometer SoCs Using On-Chip Clocking and Test Compression. Asian Test Symposium Hiroyuki Nakamura, Akio Shirokane, Yoshihito Nishizaki, Anis Uzzaman, Vivek Chickermane, Brion L. Keller, Tsutomu Ube, Yoshihiko Terauchi
2005	—	`conf`	Practical Aspects of Delay Testing for Nanometer Chips. Asian Test Symposium Vivek Chickermane, Brion L. Keller, Kevin McCauley, Anis Uzzaman
2005	A	`conf`	Use of MISRs for compression and diagnostics. ITC Brion L. Keller, Thomas Bartenstein
2004	A	`conf`	An Economic Analysis and ROI Model for Nanometer Test. ITC Brion L. Keller, Mick Tegethoff, Thomas Bartenstein, Vivek Chickermane
2004	A	`conf`	Channel Masking Synthesis for Efficient On-Chip Test Compression. ITC Vivek Chickermane, Brian Foutz, Brion L. Keller
2002	J	`jnl`	Extending OPMISR beyond 10x Scan Test Efficiency. IEEE Des. Test Comput. Carl Barnhart, Vanessa Brunkhorst, Frank Distler, Owen Farnsworth, Andrew Ferko, Brion L. Keller, David Scott, Bernd Könemann, Takeshi Onodera
2001	—	`conf`	A SmartBIST Variant with Guaranteed Encoding. Asian Test Symposium Bernd Könemann, Carl Barnhart, Brion L. Keller, Thomas J. Snethen, Owen Farnsworth, Donald L. Wheater
2001	A	`conf`	CTL the language for describing core-based test. ITC Rohit Kapur, Maurice Lousberg, Tony Taylor, Brion L. Keller, Paul Reuter, Douglas Kay
2001	C	`conf`	High Performance Parallel Fault Simulation. ICCD Amit K. Varshney, Bapiraju Vinnakota, Eric Skuldt, Brion L. Keller
2001	A	`conf`	OPMISR: the foundation for compressed ATPG vectors. ITC Carl Barnhart, Vanessa Brunkhorst, Frank Distler, Owen Farnsworth, Brion L. Keller, Bernd Könemann, Andrej Ferko
2000	A	`conf`	Design and implementation of a parallel automatic test pattern generation algorithm with low test vector count. ITC Robert Butler, Brion L. Keller, Sarala Paliwal, Richard Schoonover, Joseph Swenton
2000	—	`conf`	Effective parallel processing techniques for the generation of test data for a logic built-in self test system. Asian Test Symposium Paul Chang, Brion L. Keller, Sarala Paliwal
1999	C	`conf`	Design and Implementation of a Parallel Weighted Random Pattern and Logic Built in Self Test Algorithm. ICCD Paul Chang, Brion L. Keller, Sarala Paliwal
1999	A	`conf`	Using STIL to describe embedded core test requirements. ITC Brion L. Keller
1998	A	`conf`	ATPG in practical and non-traditional applications. ITC Brion L. Keller, Kevin McCauley, Joseph Swenton, James Youngs
1996	J	`jnl`	Test methodologies and design automation for IBM ASICs. IBM J. Res. Dev. Pamela S. Gillis, Tom S. Guzowski, Brion L. Keller, Randal H. Kerr
1992	A	`conf`	Delay Test: The Next Frontier for LSSD Test Systems. ITC Bernd Könemann, J. Barlow, Paul Chang, R. Gabrielson, C. Goertz, Brion L. Keller, Kevin McCauley, J. Tischer, Vijay S. Iyengar, Barry K. Rosen, T. Williams
1991	C	`conf`	Design Automation of Test for the EX/9000 ICCD Brion L. Keller, David A. Haynes
1991	J	`jnl`	The Compiled Logic Simulator. IEEE Des. Test Comput. Brion L. Keller, David P. Carlson, William Maloney