Brian Young

28 papers A* 1A 1B 2Journal 11Unranked 13
YearRankTypeTitle / Venue / Authors
2017 J jnl
A 5GHz Digital Fractional-N PLL Using a 1-bit Delta-Sigma Frequency-to-Digital Converter in 65 nm CMOS.
IEEE J. Solid State Circuits
Mrunmay Talegaonkar, Tejasvi Anand, Ahmed Elkholy, Amr Elshazly, Romesh Kumar Nandwana, Saurabh Saxena, Brian Young, Woo-Seok Choi, Pavan Kumar Hanumolu
2015 — conf
A 54mW 1.2GS/s 71.5dB SNDR 50MHz BW VCO-based CT ΔΣ ADC using dual phase/frequency feedback in 65nm CMOS.
VLSIC
Karthikeyan Reddy, Siladitya Dey, Sachin Rao, Brian Young, Praveen Prabha, Pavan Kumar Hanumolu
2014 — conf
A 4.4-5.4GHz digital fractional-N PLL using ΔΣ frequency-to-digital converter.
VLSIC
Mrunmay Talegaonkar, Tejasvi Anand, Ahmed Elkholy, Amr Elshazly, Romesh Kumar Nandwana, Saurabh Saxena, Brian Young, Woo-Seok Choi, Pavan Kumar Hanumolu
2014 J jnl
A 5 Gb/s, 10 ns Power-On-Time, 36 µW Off-State Power, Fast Power-On Transmitter for Energy Proportional Links.
IEEE J. Solid State Circuits
Tejasvi Anand, Amr Elshazly, Mrunmay Talegaonkar, Brian Young, Pavan Kumar Hanumolu
2014 — conf
A 75dB DR 50MHz BW 3
VLSIC
Brian Young, Karthik Reddy, Sachin Rao, Amr Elshazly, Tejasvi Anand, Pavan Kumar Hanumolu
2014 J jnl
A Deterministic Digital Background Calibration Technique for VCO-Based ADCs.
IEEE J. Solid State Circuits
Sachin Rao, Karthikeyan Reddy, Brian Young, Pavan Kumar Hanumolu
2014 J jnl
A Noise-Shaping Time-to-Digital Converter Using Switched-Ring Oscillators - Analysis, Design, and Measurement Techniques.
IEEE J. Solid State Circuits
Amr Elshazly, Sachin Rao, Brian Young, Pavan Kumar Hanumolu
2014 J jnl
A Reference-Less Clock and Data Recovery Circuit Using Phase-Rotating Phase-Locked Loop.
IEEE J. Solid State Circuits
Guanghua Shu, Saurabh Saxena, Woo-Seok Choi, Mrunmay Talegaonkar, Rajesh Inti, Amr Elshazly, Brian Young, Pavan Kumar Hanumolu
2013 — conf
A 2.5GHz 2.2mW/25µW on/off-state power 2psrms-long-term-jitter digital clock multiplier with 3-reference-cycles power-on time.
ISSCC
Tejasvi Anand, Mrunmay Talegaonkar, Amr Elshazly, Brian Young, Pavan Kumar Hanumolu
2013 — conf
Automated posteriorwall thickness measurement from B-mode ultrasound.
ISBI
Pavan Annangi, Navneeth Subramanian, Satish C. Govind, Gokul Swamy, Brian Young
2013 J jnl
Clock Multiplication Techniques Using Digital Multiplying Delay-Locked Loops.
IEEE J. Solid State Circuits
Amr Elshazly, Rajesh Inti, Brian Young, Pavan Kumar Hanumolu
2012 — conf
A 1.5GHz 890μW digital MDLL with 400fsrms integrated jitter, -55.6dBc reference spur and 20fs/mV supply-noise sensitivity using 1b TDC.
ISSCC
Amr Elshazly, Rajesh Inti, Brian Young, Pavan Kumar Hanumolu
2012 — conf
A 13b 315fsrms 2mW 500MS/s 1MHz bandwidth highly digital time-to-digital converter using switched ring oscillators.
ISSCC
Amr Elshazly, Sachin Rao, Brian Young, Pavan Kumar Hanumolu
2012 J jnl
A 16-mW 78-dB SNDR 10-MHz BW CT Delta Sigma ADC Using Residue-Cancelling VCO-Based Quantizer.
IEEE J. Solid State Circuits
Karthikeyan Reddy, Sachin Rao, Rajesh Inti, Brian Young, Amr Elshazly, Mrunmay Talegaonkar, Pavan Kumar Hanumolu
2012 — conf
A 16mW 78dB-SNDR 10MHz-BW CT-ΔΣ ADC using residue-cancelling VCO-based quantizer.
ISSCC
Karthikeyan Reddy, Sachin Rao, Rajesh Inti, Brian Young, Amr Elshazly, Mrunmay Talegaonkar, Pavan Kumar Hanumolu
2012 — conf
Quality Metric for Parasternal Long Axis B-Mode Echocardiograms.
MICCAI (2)
Sri-Kaushik Pavani, Navneeth Subramanian, Mithun Das Gupta, Pavan Annangi, Satish C. Govind, Brian Young
2011 J jnl
A 0.4-to-3 GHz Digital PLL With PVT Insensitive Supply Noise Cancellation Using Deterministic Background Calibration.
IEEE J. Solid State Circuits
Amr Elshazly, Rajesh Inti, Wenjing Yin, Brian Young, Pavan Kumar Hanumolu
2011 — conf
A 0.4-to-3GHz digital PLL with supply-noise cancellation using deterministic background calibration.
ISSCC
Amr Elshazly, Rajesh Inti, Wenjing Yin, Brian Young, Pavan Kumar Hanumolu
2011 J jnl
A 0.7-to-3.5 GHz 0.6-to-2.8 mW Highly Digital Phase-Locked Loop With Bandwidth Tracking.
IEEE J. Solid State Circuits
Wenjing Yin, Rajesh Inti, Amr Elshazly, Brian Young, Pavan Kumar Hanumolu
2011 J jnl
A TDC-Less 7 mW 2.5 Gb/s Digital CDR With Linear Loop Dynamics and Offset-Free Data Recovery.
IEEE J. Solid State Circuits
Wenjing Yin, Rajesh Inti, Amr Elshazly, Mrunmay Talegaonkar, Brian Young, Pavan Kumar Hanumolu
2011 — conf
A highly digital 0.5-to-4Gb/s 1.9mW/Gb/s serial-link transceiver using current-recycling in 90nm CMOS.
ISSCC
Rajesh Inti, Amr Elshazly, Brian Young, Wenjing Yin, Marcel A. Kossel, Thomas Toifl, Pavan Kumar Hanumolu
2010 — conf
A 2.4ps resolution 2.1mW second-order noise-shaped time-to-digital converter with 3.2ns range in 1MHz bandwidth.
CICC
Brian Young, Sunwoo Kwon, Amr Elshazly, Pavan Kumar Hanumolu
2004 B conf
Annotating Noun Argument Structure for NomBank.
LREC
Adam L. Meyers, Ruth Reeves, Catherine Macleod, Rachel Szekely, Veronika Zielinska, Brian Young, Ralph Grishman
2004 B conf
The Cross-Breeding of Dictionaries.
LREC
Adam L. Meyers, Ruth Reeves, Catherine Macleod, Rachel Szekely, Veronika Zielinska, Brian Young
2004 — conf
The NomBank Project: An Interim Report.
FCP@NAACL-HLT
Adam L. Meyers, Ruth Reeves, Catherine Macleod, Rachel Szekely, Veronika Zielinska, Brian Young, Ralph Grishman
2000 A conf
Model and analysis for combined package and on-chip power grid simulation.
ISLPED
Rajendran Panda, David T. Blaauw, Rajat Chaudhry, Vladimir Zolotov, Brian Young, Ravi Ramaraju
2000 A* conf
On-chip inductance modeling and analysis.
DAC
Kaushik Gala, Vladimir Zolotov, Rajendran Panda, Brian Young, Junfeng Wang, David T. Blaauw
1996 J jnl
Effectiveness of Individual and Dyadic Training Protocols: The Influence of Trainee Interaction Anxiety.
Hum. Factors
Winfred Arthur, Brian Young, Jeffrey A. Jordan, Wayne L. Shebilske