Brian T. Murray

25 papers A 5B 2C 1Misc 2Journal 13Unranked 1
YearRankTypeTitle / Venue / Authors
2005 J jnl
Dependable communication synthesis for distributed embedded systems.
Reliab. Eng. Syst. Saf.
Nagarajan Kandasamy, John P. Hayes, Brian T. Murray
2005 J jnl
Time-Constrained Failure Diagnosis in Distributed Embedded Systems: Application to Actuator Diagnosis.
IEEE Trans. Parallel Distributed Syst.
Nagarajan Kandasamy, John P. Hayes, Brian T. Murray
2003 B conf
Dependable Communication Synthesis for Distributed Embedded Systems.
SAFECOMP
Nagarajan Kandasamy, John P. Hayes, Brian T. Murray
2003 C conf
Low-Cost On-Line Fault Detection Using Control Flow Assertions.
IOLTS
Rajesh Venkatasubramanian, John P. Hayes, Brian T. Murray
2002 A conf
Time-Constrained Failure Diagnosis in Distributed Embedded Systems.
DSN
Nagarajan Kandasamy, John P. Hayes, Brian T. Murray
2000 J jnl
Deterministic built-in test pattern generation for high-performance circuits using twisted-ring counters.
IEEE Trans. Very Large Scale Integr. Syst.
Krishnendu Chakrabarty, Brian T. Murray, Vikram Iyengar
2000 — conf
Providing convincing evidence of safety in X-by-wire automotive systems.
HASE
Barbara J. Czerny, Joseph G. D'Ambrosio, Brian T. Murray
1999 Misc conf
Built-in Test Pattern Generation For High-Performance Cir cuits Using Twisted-Ring Counters.
VTS
Krishnendu Chakrabarty, Brian T. Murray, Vikram Iyengar
1999 J jnl
Deterministic Built-in Pattern Generation for Sequential Circuits.
J. Electron. Test.
Vikram Iyengar, Krishnendu Chakrabarty, Brian T. Murray
1999 B conf
Tolerating Transient Faults in Statically Scheduled Safety-Critical Embedded Systems.
SRDS
Nagarajan Kandasamy, John P. Hayes, Brian T. Murray
1998 Misc conf
Built-In Self Testing of Sequential Circuits Using Precomputed Test Sets.
VTS
Vikram Iyengar, Krishnendu Chakrabarty, Brian T. Murray
1998 J jnl
Design of built-in test generator circuits using width compression.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Krishnendu Chakrabarty, Brian T. Murray
1998 J jnl
Huffman encoding of test sets for sequential circuits.
IEEE Trans. Instrum. Meas.
Vikram Iyengar, Krishnendu Chakrabarty, Brian T. Murray
1998 J jnl
Online BIST for Embedded Systems.
IEEE Des. Test Comput.
Hussain Al-Asaad, Brian T. Murray, John P. Hayes
1998 J jnl
Optimal Zero-Aliasing Space Compaction of Test Responses.
IEEE Trans. Computers
Krishnendu Chakrabarty, Brian T. Murray, John P. Hayes
1998 J jnl
Scalable Test Generators for High-Speed Datapath Circuits.
J. Electron. Test.
Hussain Al-Asaad, John P. Hayes, Brian T. Murray
1997 A conf
Test Width Compression for Built-In Self Testing.
ITC
Krishnendu Chakrabarty, Jian Liu, Minyao Zhu, Brian T. Murray
1996 J jnl
Testing ICs: Getting to the Core of the Problem.
Computer
Brian T. Murray, John P. Hayes
1995 A conf
Optimal Space Compaction of Test Responses.
ITC
Krishnendu Chakrabarty, Brian T. Murray, John P. Hayes
1994 J jnl
Codesign of architectures for automotive powertrain modules.
IEEE Micro
Xiaobo Hu, Joseph G. D'Ambrosio, Brian T. Murray, Dah-Lain Tang
1994 — —
Hierarchical testing using precomputed tests for modules.
Brian T. Murray
1991 A conf
Test Propagation Through Modules and Circuits.
ITC
Brian T. Murray, John P. Hayes
1990 J jnl
Hierarchical test generation using precomputed tests for modules.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Brian T. Murray, John P. Hayes
1989 J jnl
High-Level Test Generation for VLSI.
Computer
Debashis Bhattacharya, Brian T. Murray, John P. Hayes
1988 A conf
Hierarchical Test Generation Using Precomputed Tests for Modules.
ITC
Brian T. Murray, John P. Hayes