Brian P. Degnan

24 papers C 8Journal 5Unranked 10
YearRankTypeTitle / Venue / Authors
2025 — conf
Tunnel Diode I-V Measurement and Model Generation from Incomplete Data.
RFID-TA
Brian P. Degnan, Francesco Amato, Gregory D. Durgin
2025 — conf
Wirelessly-Powered Devices Using UHF ESD Energy Capture.
RFID-TA
Stewart J. Thomas, Brian P. Degnan
2020 — conf
Backscatter Ex-Nihilo: Single-component, Fully-passive Backscattering for Microcontrollers.
RFID
Stewart J. Thomas, Brian P. Degnan, Cristel Callupe Chavez, Billy Culver
2017 — conf
A better channel code than FM0 for next-generation RFID.
RFID
Gregory D. Durgin, Brian P. Degnan
2017 — conf
On the Simon Cipher 4-block key schedule as a hash.
RFID
Brian P. Degnan, Gregory D. Durgin, Suigin Maeda
2016 J jnl
Assessing Trends in Performance per Watt for Signal Processing Applications.
IEEE Trans. Very Large Scale Integr. Syst.
Brian P. Degnan, Bo Marr, Jennifer Hasler
2016 C conf
On the temperature dependence of subthreshold currents in MOS electron inversion layers, revisited.
ISCAS
Brian P. Degnan, Jennifer Hasler
2015 — conf
A 45 μW bias power, 34 dB gain reflection amplifier exploiting the tunneling effect for RFID applications.
IEEE RFID
Francesco Amato, Christopher W. Peterson, Brian P. Degnan, Gregory D. Durgin
2015 — conf
Asynchronous trigger modulation for RFID systems.
RFID-TA
Brian P. Degnan, Gregory D. Durgin
2015 — conf
Low-power, serial interface for power-constrained devices.
MWSCAS
Brian P. Degnan, Jennifer Hasler
2013 J jnl
A Learning-Enabled Neuron Array IC Based Upon Transistor Channel Models of Biological Phenomena.
IEEE Trans. Biomed. Circuits Syst.
Stephen Brink, Stephen Nease, Paul E. Hasler, Shubha Ramakrishnan, Richard B. Wunderlich, Arindam Basu, Brian P. Degnan
2013 J jnl
Scaling Energy Per Operation via an Asynchronous Pipeline.
IEEE Trans. Very Large Scale Integr. Syst.
Bo Marr, Brian P. Degnan, Paul E. Hasler, David V. Anderson
2013 — —
Temperature robust programmable subthreshold circuits through a balanced force approach.
Brian P. Degnan
2010 C conf
Crossbar switch matrix for floating-gate programming over large current ranges.
ISCAS
Brian P. Degnan, Brian J. Duffy, Paul E. Hasler
2010 J jnl
Error Immune Logic for Low-Power Probabilistic Computing.
VLSI Design
Bo Marr, Jason George, Brian P. Degnan, David V. Anderson, Paul E. Hasler
2010 C conf
Hardware and software infrastructure for a family of floating-gate based FPAAs.
ISCAS
Scott Koziol, Craig Schlottmann, Arindam Basu, Stephen Brink, Csaba Petre, Brian P. Degnan, Shubha Ramakrishnan, Paul E. Hasler, Aurele Balavoine
2010 C conf
Live demonstration: Hardware and software infrastructure for a family of floating-gate based FPAAs.
ISCAS
Scott Koziol, Craig Schlottmann, Arindam Basu, Stephen Brink, Csaba Petre, Brian P. Degnan, Shubha Ramakrishnan, Paul E. Hasler, Aurele Balavoine
2010 C conf
Reducing offset errors in MITE systems by precise floating gate programming.
ISCAS
Craig Schlottmann, Brian P. Degnan, David Abramson, Paul E. Hasler
2009 C conf
An Asynchronously Embedded Datapath for Performance Acceleration and Energy Efficiency.
ISCAS
Bo Marr, Brian P. Degnan, Paul E. Hasler, David V. Anderson
2009 C conf
Passgate Resistance Estimation based on the Compact EKV Model and Effective Mobility.
ISCAS
Brian P. Degnan, Richard B. Wunderlich, Paul E. Hasler
2007 C conf
Capacitively-Biased Floating-Gate CMOS: a New Logic Family.
ISCAS
Richard B. Wunderlich, Brian P. Degnan, Paul E. Hasler
2007 J jnl
Indirect Programming of Floating-Gate Transistors.
IEEE Trans. Circuits Syst. I Regul. Pap.
David W. Graham, Ethan Farquhar, Brian P. Degnan, Christal Gordon, Paul E. Hasler
2005 — conf
Indirect programming of floating-gate transistors.
ISCAS (3)
David W. Graham, Ethan Farquhar, Brian P. Degnan, Christal Gordon, Paul E. Hasler
2005 — conf
Programmable floating-gate techniques for CMOS inverters.
ISCAS (3)
Brian P. Degnan, Richard B. Wunderlich, Paul E. Hasler