Brian Cline

42 papers A* 5A 11C 2Journal 14Unranked 10
YearRankTypeTitle / Venue / Authors
2022 J jnl
Design-Aware Partitioning-Based 3-D IC Design Flow With 2-D Commercial Tools.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Kyungwook Chang, Saurabh Sinha, Brian Cline, Greg Yeric, Sung Kyu Lim
2022 — conf
System technology co-optimization and design challenges for 3D IC.
CICC
Supreet Jeloka, Brian Cline, Shidhartha Das, Benoit Labbe, Alejandro Rico, Rainer Herberholz, Javier A. DeLaCruz, Rahul Mathur, Shawn Hung
2021 — conf
3D-Split SRAM: Enabling Generational Gains in Advanced CMOS.
CICC
Rahul Mathur, Mudit Bhargava, Heath Perry, Alberto Cestero, Frank Frederick, Shawn Hung, Chien-Ju Chao, Daniel Smith, Daniel Fisher, Norman Robson, Xiaoqing Xu, Pranavi Chandupatla, Raguram Balachandran, Saurabh Sinha, Brian Cline, Jaydeep P. Kulkarni
2021 — conf
A 64-Bit Arm CPU at Cryogenic temperatures: Design Technology Co-Optimization for Power and Performance.
CICC
Rakshith Saligram, Divya Prasad, David Pietromonaco, Arijit Raychowdhury, Brian Cline
2021 J jnl
Device-to-System Performance Evaluation: from Transistor/Interconnect Modeling to VLSI Physical Design and Neural-Network Predictor.
CoRR
Chi-Shuen Lee, Brian Cline, Saurabh Sinha, Greg Yeric, H.-S. Philip Wong
2021 J jnl
High-Performance Logic-on-Memory Monolithic 3-D IC Designs for Arm Cortex-A Processors.
IEEE Trans. Very Large Scale Integr. Syst.
Lingjun Zhu, Lennart Bamberg, Sai Surya Kiran Pentapati, Kyungwook Chang, Francky Catthoor, Dragomir Milojevic, Manu Komalan, Brian Cline, Saurabh Sinha, Xiaoqing Xu, Alberto García-Ortiz, Sung Kyu Lim
2021 A conf
Power Delivery and Thermal-Aware Arm-Based Multi-Tier 3D Architecture.
ISLPED
Lingjun Zhu, Tuan Ta, Rossana Liu, Rahul Mathur, Xiaoqing Xu, Shidhartha Das, Ankit Kaul, Alejandro Rico, Doug Joseph, Brian Cline, Sung Kyu Lim
2020 J jnl
Stack up your chips: Betting on 3D integration to augment Moore's Law scaling.
CoRR
Saurabh Sinha, Xiaoqing Xu, Mudit Bhargava, Shidhartha Das, Brian Cline, Greg Yeric
2019 A conf
Enhanced 3D Implementation of an Arm
ISLPED
Xiaoqing Xu, Mudit Bhargava, Steve Moore, Saurabh Sinha, Brian Cline
2019 J jnl
System-Level Power Delivery Network Analysis and Optimization for Monolithic 3-D ICs.
IEEE Trans. Very Large Scale Integr. Syst.
Kyungwook Chang, Shidhartha Das, Saurabh Sinha, Brian Cline, Greg Yeric, Sung Kyu Lim
2018 A* conf
Accurate processor-level wirelength distribution model for technology pathfinding using a modernized interpretation of rent's rule.
DAC
Divya Prasad, Saurabh Sinha, Brian Cline, Steve Moore, Azad Naeemi
2018 J jnl
Standard Cell Library Design and Optimization Methodology for ASAP7 PDK.
CoRR
Xiaoqing Xu, Nishi Shah, Andrew Evans, Saurabh Sinha, Brian Cline, Greg Yeric
2017 C conf
DTCO for DSA-MP Hybrid Lithography with Double-BCP Materials in Sub-7nm Node.
ICCD
Jiaojiao Ou, Xiaoqing Xu, Brian Cline, Greg Yeric, David Z. Pan
2017 A conf
Frequency and time domain analysis of power delivery network for monolithic 3D ICs.
ISLPED
Kyungwook Chang, Shidhartha Das, Saurabh Sinha, Brian Cline, Greg Yeric, Sung Kyu Lim
2017 J jnl
Impact and Design Guideline of Monolithic 3-D IC at the 7-nm Technology Node.
IEEE Trans. Very Large Scale Integr. Syst.
Kyungwook Chang, Kartik Acharya, Saurabh Sinha, Brian Cline, Greg Yeric, Sung Kyu Lim
2017 J jnl
Impact of FinFET on Near-Threshold Voltage Scalability.
IEEE Des. Test
Nathaniel Ross Pinckney, Supreet Jeloka, Ronald G. Dreslinski, Trevor N. Mudge, Dennis Sylvester, David T. Blaauw, Lucian Shifren, Brian Cline, Saurabh Sinha
2017 J jnl
Redundant Local-Loop Insertion for Unidirectional Routing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Xiaoqing Xu, Yibo Lin, Meng Li, Jiaojiao Ou, Brian Cline, David Z. Pan
2017 A conf
Standard cell library design and optimization methodology for ASAP7 PDK: (Invited paper).
ICCAD
Xiaoqing Xu, Nishi Shah, Andrew Evans, Saurabh Sinha, Brian Cline, Greg Yeric
2016 J jnl
ASAP7: A 7-nm finFET predictive process design kit.
Microelectron. J.
Lawrence T. Clark, Vinay Vashishtha, Lucian Shifren, Aditya Gujja, Saurabh Sinha, Brian Cline, Chandarasekaran Ramamurthy, Greg Yeric
2016 A conf
Cascade2D: A design-aware partitioning approach to monolithic 3D IC with 2D commercial tools.
ICCAD
Kyungwook Chang, Saurabh Sinha, Brian Cline, Raney Southerland, Michael Doherty, Greg Yeric, Sung Kyu Lim
2016 A conf
Four-tier Monolithic 3D ICs: Tier Partitioning Methodology and Power Benefit Study.
ISLPED
Kwang Min Kim, Saurabh Sinha, Brian Cline, Greg Yeric, Sung Kyu Lim
2016 A* conf
Match-making for monolithic 3D IC: finding the right technology node.
DAC
Kyungwook Chang, Saurabh Sinha, Brian Cline, Greg Yeric, Sung Kyu Lim
2016 — conf
Monolithic 3D IC design: Power, performance, and area impact at 7nm.
ISQED
Kartik Acharya, Kyungwook Chang, Bon Woong Ku, Shreepad Panth, Saurabh Sinha, Brian Cline, Greg Yeric, Sung Kyu Lim
2016 A* conf
Near-threshold computing in FinFET technologies: opportunities for improved voltage scalability.
DAC
Nathaniel Ross Pinckney, Lucian Shifren, Brian Cline, Saurabh Sinha, Supreet Jeloka, Ronald G. Dreslinski, Trevor N. Mudge, Dennis Sylvester, David T. Blaauw
2016 J jnl
Predicting future complementary metal-oxide-semiconductor technology - challenges and approaches.
IET Comput. Digit. Tech.
Robert C. Aitken, Vikas Chandra, Brian Cline, Shidhartha Das, David Pietromonaco, Lucian Shifren, Saurabh Sinha, Greg Yeric
2016 — conf
Welcome.
ISQED
Brian Cline, Saibal Mukhopadhyay, Peter J. Wright, Hai Li, Vinod Viswanath, Paul Wesling, Gang Qu, Ali Iranmanesh
2015 — conf
Circuit design perspectives for Ge FinFET at 10nm and beyond.
ISQED
Saurabh Sinha, Lucian Shifren, Vikas Chandra, Brian Cline, Greg Yeric, Robert C. Aitken, Bingjie Cheng, Andrew R. Brown, Craig Riddet, C. Alexandar, Campbell Millar, Asen Asenov
2015 A conf
Power benefit study of monolithic 3D IC at the 7nm technology node.
ISLPED
Kyungwook Chang, Kartik Acharya, Saurabh Sinha, Brian Cline, Greg Yeric, Sung Kyu Lim
2015 J jnl
Self-Aligned Double Patterning Aware Pin Access and Standard Cell Layout Co-Optimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Xiaoqing Xu, Brian Cline, Greg Yeric, Bei Yu, David Z. Pan
2014 C conf
DFM is dead - Long live DFM.
ICCD
Robert C. Aitken, David Pietromonaco, Brian Cline
2014 — conf
Physical design and FinFETs.
ISPD
Robert C. Aitken, Greg Yeric, Brian Cline, Saurabh Sinha, Lucian Shifren, Imran Iqbal, Vikas Chandra
2014 — conf
Self-aligned double patterning aware pin access and standard cell layout co-optimization.
ISPD
Xiaoqing Xu, Brian Cline, Greg Yeric, Bei Yu, David Z. Pan
2013 — conf
The past present and future of design-technology co-optimization.
CICC
Greg Yeric, Brian Cline, Saurabh Sinha, David Pietromonaco, Vikas Chandra, Rob Aitken
2012 A conf
Design benchmarking to 7nm with FinFET predictive technology models.
ISLPED
Saurabh Sinha, Brian Cline, Greg Yeric, Vikas Chandra, Yu Cao
2012 A* conf
Exploring sub-20nm FinFET design with predictive technology models.
DAC
Saurabh Sinha, Greg Yeric, Vikas Chandra, Brian Cline, Yu Cao
2010 J jnl
Mechanical Stress Aware Optimization for Leakage Power Reduction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Vivek Joshi, Brian Cline, Dennis Sylvester, David T. Blaauw, Kanak Agarwal
2008 J jnl
Exploring Variability and Performance in a Sub-200-mV Processor.
IEEE J. Solid State Circuits
Scott Hanson, Bo Zhai, Mingoo Seok, Brian Cline, Kevin Zhou, Meghna Singhal, Michael Minuth, Javin Olson, Leyla Nazhandali, Todd M. Austin, Dennis Sylvester, David T. Blaauw
2008 A* conf
Leakage power reduction using stress-enhanced layouts.
DAC
Vivek Joshi, Brian Cline, Dennis Sylvester, David T. Blaauw, Kanak Agarwal
2008 A conf
STEEL: a technique for stress-enhanced standard cell library design.
ICCAD
Brian Cline, Vivek Joshi, Dennis Sylvester, David T. Blaauw
2008 — conf
Stress aware layout optimization.
ISPD
Vivek Joshi, Brian Cline, Dennis Sylvester, David T. Blaauw, Kanak Agarwal
2008 A conf
Transistor-Specific Delay Modeling for SSTA.
DATE
Brian Cline, Kaviraj Chopra, David T. Blaauw, Andres Torres, Savithri Sundareswaran
2006 A conf
Analysis and modeling of CD variation for statistical static timing.
ICCAD
Brian Cline, Kaviraj Chopra, David T. Blaauw, Yu Cao