Brett H. Meyer

93 papers A* 3A 10B 1C 5Misc 8Journal 39Unranked 27
YearRankTypeTitle / Venue / Authors
2026 J jnl
Efficient CMOS Invertible Logic Using Stochastic Computing.
CoRR
Sean C. Smithson, Naoya Onizawa, Brett H. Meyer, Warren J. Gross, Takahiro Hanyu
2025 — conf
AdCorDA: Classifier Refinement via Adversarial Correction and Domain Adaptation.
ICCVW
Lulan Shen, Ali Edalati, Xiangyu Li, Brett H. Meyer, Warren J. Gross, James J. Clark
2024 J jnl
AdCorDA: Classifier Refinement via Adversarial Correction and Domain Adaptation.
CoRR
Lulan Shen, Ali Edalati, Brett H. Meyer, Warren J. Gross, James J. Clark
2024 — conf
Automatic Pruning of Fine-tuning Datasets for Transformer-based Language Models.
CoLLAs
Sayed Mohammadreza Tayaranian Hosseini, Seyyed Hasan Mozafari, Brett H. Meyer, James J. Clark, Warren J. Gross
2024 J jnl
Automatic Pruning of Fine-tuning Datasets for Transformer-based Language Models.
CoRR
Mohammadreza Tayaranian, Seyyed Hasan Mozafari, Brett H. Meyer, James J. Clark, Warren J. Gross
2024 J jnl
Faster Inference of Integer SWIN Transformer by Removing the GELU Activation.
CoRR
Mohammadreza Tayaranian, Seyyed Hasan Mozafari, James J. Clark, Brett H. Meyer, Warren J. Gross
2024 — conf
Intermediate Layer Distillation with the Reused Teacher Classifier: A Study on the Importance of the Classifier of Attention-based Models.
EMNLP (Findings)
Hang Zhang, Seyyed Hasan Mozafari, James J. Clark, Brett H. Meyer, Warren J. Gross
2024 — conf
Parameter Efficient Fine-tuning of Transformer-Based Language Models Using Dataset Pruning.
IEEECONF
Sayed Mohammadreza Tayaranian Hosseini, Seyyed Hasan Mozafari, James Clark, Brett H. Meyer, Warren J. Gross
2024 J jnl
Robustness to distribution shifts of compressed networks for edge devices.
CoRR
Lulan Shen, Ali Edalati, Brett H. Meyer, Warren J. Gross, James J. Clark
2023 J jnl
DT-DS: CAN Intrusion Detection with Decision Tree Ensembles.
ACM Trans. Cyber Phys. Syst.
Jarul Mehta, Guillaume Richard, Loren Lugosch, Derek Yu, Brett H. Meyer
2023 — conf
Efficient 1D Grouped Convolution for PyTorch a Case Study: Fast On-Device Fine-Tuning for SqueezeBERT.
ASAP
Seyyed Hasan Mozafari, James J. Clark, Warren J. Gross, Brett H. Meyer
2023 J jnl
FMAS: Fast Multi-Objective SuperNet Architecture Search for Semantic Segmentation.
CoRR
Zhuoran Xiong, Marihan Amein, Olivier Therrien, Warren J. Gross, Brett H. Meyer
2023 — conf
Fast Fine-Tuning Using Curriculum Domain Adaptation.
CRV
Lulan Shen, Ibtihel Amara, Ruofeng Li, Brett H. Meyer, Warren J. Gross, James J. Clark
2023 — conf
High-Throughput Edge Inference for BERT Models via Neural Architecture Search and Pipeline.
ACM Great Lakes Symposium on VLSI
Hung-Yang Chang, Seyyed Hasan Mozafari, James J. Clark, Brett H. Meyer, Warren J. Gross
2023 J jnl
PipeBERT: High-throughput BERT Inference for ARM Big.LITTLE Multi-core Processors.
J. Signal Process. Syst.
Hung-Yang Chang, Seyyed Hasan Mozafari, Cheng Chen, James J. Clark, Brett H. Meyer, Warren J. Gross
2023 J jnl
SSS3D: Fast Neural Architecture Search For Efficient Three-Dimensional Semantic Segmentation.
CoRR
Olivier Therrien, Marihan Amein, Zhuoran Xiong, Warren J. Gross, Brett H. Meyer
2023 C conf
Training Acceleration of Frequency Domain CNNs Using Activation Compression.
ISCAS
Seyyed Hasan Mozafari, James J. Clark, Warren J. Gross, Brett H. Meyer
2022 J jnl
BD-KD: Balancing the Divergences for Online Knowledge Distillation.
CoRR
Ibtihel Amara, Nazanin Mohammadi Sepahvand, Brett H. Meyer, Warren J. Gross, James J. Clark
2022 — conf
BERTPerf: Inference Latency Predictor for BERT on ARM big.LITTLE Multi-Core Processors.
SiPS
M. Abdelgawad, Seyyed Hasan Mozafari, James J. Clark, Brett H. Meyer, Warren J. Gross
2022 B conf
CES-KD: Curriculum-based Expert Selection for Guided Knowledge Distillation.
ICPR
Ibtihel Amara, Maryam Ziaeefard, Brett H. Meyer, Warren J. Gross, James J. Clark
2022 J jnl
CES-KD: Curriculum-based Expert Selection for Guided Knowledge Distillation.
CoRR
Ibtihel Amara, Maryam Ziaeefard, Brett H. Meyer, Warren J. Gross, James J. Clark
2022 — conf
Conjugate Adder Net (CAddNet) - a Space-Efficient Approximate CNN.
CVPR Workshops
Lulan Shen, Maryam Ziaeefard, Brett H. Meyer, Warren J. Gross, James J. Clark
2022 C conf
Efficient Fine-Tuning of BERT Models on the Edge.
ISCAS
Danilo Vucetic, Mohammadreza Tayaranian, Maryam Ziaeefard, James J. Clark, Brett H. Meyer, Warren J. Gross
2022 J jnl
Efficient Fine-Tuning of BERT Models on the Edge.
CoRR
Danilo Vucetic, Mohammadreza Tayaranian, Maryam Ziaeefard, James J. Clark, Brett H. Meyer, Warren J. Gross
2022 J jnl
Efficient Fine-Tuning of Compressed Language Models with Learners.
CoRR
Danilo Vucetic, Mohammadreza Tayaranian, Maryam Ziaeefard, James J. Clark, Brett H. Meyer, Warren J. Gross
2022 — conf
Fast Heterogeneous Task Mapping for Reducing Edge DNN Latency.
ASAP
Murray L. Kornelsen, Seyyed Hasan Mozafari, James J. Clark, Brett H. Meyer, Warren J. Gross
2022 J jnl
Standard Deviation-Based Quantization for Deep Neural Networks.
CoRR
Amir Ardakani, Arash Ardakani, Brett H. Meyer, James J. Clark, Warren J. Gross
2022 Misc conf
Work-in-Progress: SuperNAS: Fast Multi-Objective SuperNet Architecture Search for Semantic Segmentation.
CASES
Marihan Amein, Zhuoran Xiong, Olivier Therrien, Brett H. Meyer, Warren J. Gross
2022 Misc conf
Work-in-Progress: Utilizing latency and accuracy predictors for efficient hardware-aware NAS.
CODES+ISSS
Negin Firouzian, Seyyed Hasan Mozafari, James J. Clark, Warren J. Gross, Brett H. Meyer
2021 J jnl
A Design Framework for Invertible Logic.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Naoya Onizawa, Kaito Nishino, Sean C. Smithson, Brett H. Meyer, Warren J. Gross, Hitoshi Yamagata, Hiroyuki Fujita, Takahiro Hanyu
2021 J jnl
Hardware-Aware Design for Edge Intelligence.
IEEE Open J. Circuits Syst.
Warren J. Gross, Brett H. Meyer, Arash Ardakani
2021 — conf
Hartley Stochastic Computing For Convolutional Neural Networks.
SiPS
Seyyed Hasan Mozafari, James J. Clark, Warren J. Gross, Brett H. Meyer
2021 J jnl
Implementing Convolutional Neural Networks Using Hartley Stochastic Computing With Adaptive Rate Feature Map Compression.
IEEE Open J. Circuits Syst.
Seyyed Hasan Mozafari, James J. Clark, Warren J. Gross, Brett H. Meyer
2021 J jnl
Worst-Case Execution Time Calculation for Query-Based Monitors by Witness Generation.
CoRR
Márton Búr, Kristóf Marussy, Brett H. Meyer, Dániel Varró
2021 J jnl
Worst-case Execution Time Calculation for Query-based Monitors by Witness Generation.
ACM Trans. Embed. Comput. Syst.
Márton Búr, Kristóf Marussy, Brett H. Meyer, Dániel Varró
2020 J jnl
Hot sparing for lifetime-chip-performance and cost improvement in application specific SIMT processors.
Des. Autom. Embed. Syst.
Seyyed Hasan Mozafari, Brett H. Meyer
2020 J jnl
In-Hardware Training Chip Based on CMOS Invertible Logic for Machine Learning.
IEEE Trans. Circuits Syst. I Fundam. Theory Appl.
Naoya Onizawa, Sean C. Smithson, Brett H. Meyer, Warren J. Gross, Takahiro Hanyu
2020 A conf
Probabilistic Sequential Multi-Objective Optimization of Convolutional Neural Networks.
DATE
Zixuan Yin, Warren J. Gross, Brett H. Meyer
2020 J jnl
Surprisal-Triggered Conditional Computation with Neural Networks.
CoRR
Loren Lugosch, Derek Nowrouzezahrai, Brett H. Meyer
2020 Misc conf
Using Speech Synthesis to Train End-To-End Spoken Language Understanding Models.
ICASSP
Loren Lugosch, Brett H. Meyer, Derek Nowrouzezahrai, Mirco Ravanelli
2019 Misc conf
A Design Framework for Invertible Logic.
ACSSC
Naoya Onizawa, Kaito Nishino, Sean C. Smithson, Brett H. Meyer, Warren J. Gross, Hitoshi Yamagata, Hiroyuki Fujita, Takahiro Hanyu
2019 C conf
ARINC-825TBv2: A Hardware-in-the-Ioop Simulation Platform for Aerospace Security Research.
RSP
Derek Yu, Michael Vaquier, Evan Laflamme, Gabrielle Doucette-Poirier, Justin Tremblay, Brett H. Meyer
2019 J jnl
Characterizing the Effectiveness of Hot Sparing on Cost and Performance-per-Watt in Application Specific SIMT.
Integr.
Seyyed Hasan Mozafari, Brett H. Meyer
2019 J jnl
Efficient CMOS Invertible Logic Using Stochastic Computing.
IEEE Trans. Circuits Syst. I Regul. Pap.
Sean C. Smithson, Naoya Onizawa, Brett H. Meyer, Warren J. Gross, Takahiro Hanyu
2019 — conf
Learning Recurrent Binary/Ternary Weights.
ICLR (Poster)
Arash Ardakani, Zhengyun Ji, Sean C. Smithson, Brett H. Meyer, Warren J. Gross
2019 J jnl
Partitioning and Selection of Data Consistency Mechanisms for Multicore Real-Time Systems.
ACM Trans. Embed. Comput. Syst.
Zaid Al-bayati, Youcheng Sun, Haibo Zeng, Marco Di Natale, Qi Zhu, Brett H. Meyer
2018 J jnl
Efficient Performance Evaluation of Multi-Core SIMT Processors with Hot Redundancy.
IEEE Trans. Emerg. Top. Comput.
Seyyed Hasan Mozafari, Brett H. Meyer
2018 J jnl
Learning Recurrent Binary/Ternary Weights.
CoRR
Arash Ardakani, Zhengyun Ji, Sean C. Smithson, Brett H. Meyer, Warren J. Gross
2018 J jnl
Mapping and Scheduling Mixed-Criticality Systems with On-Demand Redundancy.
IEEE Trans. Computers
Jonah Caplan, Zaid Al-bayati, Haibo Zeng, Brett H. Meyer
2018 — conf
Study of Stochastic Invertible Multiplier Designs.
ICECS
Kaito Nishino, Sean C. Smithson, Naoya Onizawa, Brett H. Meyer, Warren J. Gross, Hitoshi Yamagata, Hiroyuki Fujita, Takahiro Hanyu
2017 J jnl
Area, Throughput, and Power Trade-Offs for FPGA- and ASIC-Based Execution Stream Compression.
ACM Trans. Embed. Comput. Syst.
Maria Isabel Mera, Jonah Caplan, Seyyed Hasan Mozafari, Brett H. Meyer, Peter A. Milder
2017 A conf
Multi-armed bandits for efficient lifetime estimation in MPSoC design.
DATE
Calvin Ma, Aditya Mahajan, Brett H. Meyer
2016 A conf
A four-mode model for efficient fault-tolerant mixed-criticality systems.
DATE
Zaid Al-bayati, Jonah Caplan, Brett H. Meyer, Haibo Zeng
2016 — conf
Bounding error detection latency in safety critical systems with enhanced Execution Fingerprinting.
DFT
Mojing Liu, Brett H. Meyer
2016 — conf
Capturing True Workload Dependency of BTI-induced Degradation in CPU Components.
ACM Great Lakes Symposium on VLSI
Dimitrios Stamoulis, Simone Corbetta, Dimitrios Rodopoulos, Pieter Weckx, Peter Debacker, Brett H. Meyer, Ben Kaczer, Praveen Raghavan, Dimitrios Soudris, Francky Catthoor, Zeljko Zilic
2016 — conf
Fault-tolerant scheduling of multicore mixed-criticality systems under permanent failures.
DFT
Zaid Al-bayati, Brett H. Meyer, Haibo Zeng
2016 J jnl
Neural Networks Designing Neural Networks: Multi-Objective Hyper-Parameter Optimization.
CoRR
Sean C. Smithson, Guang Yang, Warren J. Gross, Brett H. Meyer
2016 A conf
Neural networks designing neural networks: multi-objective hyper-parameter optimization.
ICCAD
Sean C. Smithson, Guang Yang, Warren J. Gross, Brett H. Meyer
2016 — conf
Sparse-Clustered Network with Selective Decoding for Internet Traffic Classification.
SiPS
Scott Dickson Dagondon, Warren J. Gross, Brett H. Meyer
2016 — conf
Stochastic Computing Can Improve Upon Digital Spiking Neural Networks.
SiPS
Sean C. Smithson, Kaushik Boga, Arash Ardakani, Brett H. Meyer, Warren J. Gross
2016 J jnl
Tolerating the Consequences of Multiple EM-Induced C4 Bump Failures.
IEEE Trans. Very Large Scale Integr. Syst.
Runjie Zhang, Brett H. Meyer, Ke Wang, Mircea R. Stan, Kevin Skadron
2015 — conf
A co-design approach for fault-tolerant loop execution on Coarse-Grained Reconfigurable Arrays.
AHS
Vahid Lari, Alexandru Tanase, Jürgen Teich, Michael Witterauf, Faramarz Khosravi, Frank Hannig, Brett H. Meyer
2015 A* conf
A cross-layer design exploration of charge-recycled power-delivery in many-layer 3d-IC.
DAC
Runjie Zhang, Kaushik Mazumdar, Brett H. Meyer, Ke Wang, Kevin Skadron, Mircea R. Stan
2015 — conf
Efficient Reliability Analysis of Processor Datapath using Atomistic BTI Variability Models.
ACM Great Lakes Symposium on VLSI
Dimitrios Stamoulis, Dimitrios Rodopoulos, Brett H. Meyer, Dimitrios Soudris, Francky Catthoor, Zeljko Zilic
2015 — conf
Hot spare components for performance-cost improvement in multi-core SIMT.
DFTS
Seyyed Hasan Mozafari, Brett H. Meyer
2015 — conf
RotR: Rotational redundant task mapping for fail-operational MPSoCs.
DFTS
Badrun Nahar, Brett H. Meyer
2015 A conf
Task placement and selection of data consistency mechanisms for real-time multicore applications.
RTAS
Zaid Al-bayati, Youcheng Sun, Haibo Zeng, Marco Di Natale, Qi Zhu, Brett H. Meyer
2015 J jnl
Techniques for on-demand structural redundancy for massively parallel processor arrays.
J. Syst. Archit.
Vahid Lari, Jürgen Teich, Alexandru Tanase, Michael Witterauf, Faramarz Khosravi, Brett H. Meyer
2015 A conf
Transient voltage noise in charge-recycled power delivery networks for many-layer 3D-IC.
ISLPED
Runjie Zhang, Kaushik Mazumdar, Brett H. Meyer, Ke Wang, Kevin Skadron, Mircea R. Stan
2015 — conf
Yield-aware Performance-Cost Characterization for Multi-Core SIMT.
ACM Great Lakes Symposium on VLSI
Seyyed Hasan Mozafari, Brett H. Meyer, Kevin Skadron
2014 A* conf
Architecture implications of pads as a scarce resource.
ISCA
Runjie Zhang, Ke Wang, Brett H. Meyer, Mircea R. Stan, Kevin Skadron
2014 J jnl
Cost-effective lifetime and yield optimization for NoC-based MPSoCs.
ACM Trans. Design Autom. Electr. Syst.
Brett H. Meyer, Adam S. Hartman, Donald E. Thomas
2014 Misc conf
Flexibility and Circuit Overheads in Reconfigurable SIMD/MIMD Systems.
FCCM
Saad Arrabi, D. Moore, L. Wang, Kevin Skadron, Benton H. Calhoun, John C. Lach, Brett H. Meyer
2014 — conf
Linear regression techniques for efficient analysis of transistor variability.
ICECS
Dimitrios Stamoulis, Dimitrios Rodopoulos, Brett H. Meyer, Dimitrios Soudris, Zeljko Zilic
2014 — conf
MB-FICA: multi-bit fault injection and coverage analysis.
ACM Great Lakes Symposium on VLSI
Chen Jiang, Mojing Liu, Brett H. Meyer
2014 A conf
Trade-offs in execution signature compression for reliable processor systems.
DATE
Jonah Caplan, Maria Isabel Mera, Peter A. Milder, Brett H. Meyer
2014 A* conf
Walking Pads: Managing C4 Placement for Transient Voltage Noise Minimization.
DAC
Ke Wang, Brett H. Meyer, Runjie Zhang, Mircea R. Stan, Kevin Skadron
2014 — conf
Walking pads: Fast power-supply pad-placement optimization.
ASP-DAC
Ke Wang, Brett H. Meyer, Runjie Zhang, Kevin Skadron, Mircea R. Stan
2013 J jnl
Architectural implications of spatial thermal filtering.
Integr.
Karthik Sankaranarayanan, Brett H. Meyer, Wei Huang, Robert J. Ribando, Hossein Haj-Hariri, Mircea R. Stan, Kevin Skadron
2013 J jnl
Evaluating Overheads of Multibit Soft-Error Protection in the Processor Core.
IEEE Micro
Lukasz G. Szafaryn, Brett H. Meyer, Kevin Skadron
2012 C conf
ArchFP: Rapid prototyping of pre-RTL floorplans.
VLSI-SoC
Gregory G. Faust, Runjie Zhang, Kevin Skadron, Mircea R. Stan, Brett H. Meyer
2011 Misc conf
Cost-effective safety and fault localization using distributed temporal redundancy.
CASES
Brett H. Meyer, Benton H. Calhoun, John C. Lach, Kevin Skadron
2011 A conf
Reducing the cost of redundant execution in safety-critical systems using relaxed dedication.
DATE
Brett H. Meyer, Nishant J. George, Benton H. Calhoun, John C. Lach, Kevin Skadron
2011 J jnl
Thermal benefit of multi-core floorplanning: A limits study.
Sustain. Comput. Informatics Syst.
Karthik Sankaranarayanan, Brett H. Meyer, Mircea R. Stan, Kevin Skadron
2010 Misc conf
A case for lifetime-aware task mapping in embedded chip multiprocessors.
CODES+ISSS
Adam S. Hartman, Donald E. Thomas, Brett H. Meyer
2010 A conf
Cost-effective slack allocation for lifetime improvement in NoC-based MPSoCs.
DATE
Brett H. Meyer, Adam S. Hartman, Donald E. Thomas
2010 — conf
Slack allocation for yield improvement in NoC-based MPSoCs.
ISQED
Brett H. Meyer, Adam S. Hartman, Donald E. Thomas
2010 C conf
Temperature-to-power mapping.
ICCD
Zhenyu Qi, Brett H. Meyer, Wei Huang, Robert J. Ribando, Kevin Skadron, Mircea R. Stan
2009 J jnl
Rethinking the synthesis of buses, data mapping, and memory allocation for MPSoC.
Des. Autom. Embed. Syst.
Brett H. Meyer, Donald E. Thomas
2007 J jnl
Amdahl's Law Revisited for Single Chip Systems.
Int. J. Parallel Program.
JoAnn M. Paul, Brett H. Meyer
2007 A conf
Rethinking Automated Synthesis of MPSoC Architectures.
IPDPS
Brett H. Meyer, Donald E. Thomas
2007 Misc conf
Simultaneous synthesis of buses, data mapping and memory allocation for MPSoC.
CODES+ISSS
Brett H. Meyer, Donald E. Thomas
2005 J jnl
Power-Performance Simulation and Design Strategies for Single-Chip Heterogeneous Multiprocessors.
IEEE Trans. Computers
Brett H. Meyer, Joshua J. Pieper, JoAnn M. Paul, Jeffrey E. Nelson, Sean M. Pieper, Anthony G. Rowe