Brent E. Nelson

78 papers A* 2A 5B 23C 1Misc 17Journal 16Unranked 14

Year	Rank	Type	Title / Venue / Authors
2019	Misc	`conf`	Maverick: A Stand-Alone CAD Flow for Partially Reconfigurable FPGA Modules. FCCM Dallon Glick, Jesse Grigg, Brent E. Nelson, Michael J. Wirthlin
2019	A	`conf`	Maverick: A Stand-alone CAD Flow for Xilinx 7-Series FPGAs. FPGA Dallon Glick, Jesse Grigg, Brent E. Nelson, Michael J. Wirthlin
2019	—	`conf`	Third Party CAD Tools for FPGA Design - A Survey of the Current Landscape. ARC Brent E. Nelson
2017	B	`conf`	Vivado design interface: An export/import capability for Vivado FPGA designs. FPL Thomas Townsend, Brent E. Nelson
2016	B	`conf`	An XDL alternative for interfacing RapidSmith and Vivado. FPL Thomas Townsend, Brent E. Nelson, Michael J. Wirthlin
2016	B	`conf`	Efficient processing of phased array radar in sense and avoid application using heterogeneous computing. FPL Luke Newmeyer, Doran Wilde, Brent E. Nelson, Michael J. Wirthlin
2016	—	`conf`	Packing a modern Xilinx FPGA using RapidSmith. ReConFig Travis Haroldsen, Brent E. Nelson, Brad L. Hutchings
2015	A	`conf`	RapidSmith 2: A Framework for BEL-level CAD Exploration on Xilinx FPGAs. FPGA Travis Haroldsen, Brent E. Nelson, Brad L. Hutchings
2014	—	`conf`	Tincr - A custom CAD tool framework for Vivado. ReConFig Brad White, Brent E. Nelson
2013	B	`conf`	Impact of hard macro size on FPGA clock rate and place/route time. FPL Christopher Lavin, Brent E. Nelson, Brad L. Hutchings
2013	—	`conf`	Improving clock-rate of hard-macro designs. FPT Christopher Lavin, Brent E. Nelson, Brad L. Hutchings
2013	B	`conf`	Rapid FPGA design prototyping through preservation of system logic: A case study. FPL Travis Haroldsen, Brent E. Nelson, Brad White
2011	Misc	`conf`	HMFlow: Accelerating FPGA Compilation with Hard Macros for Rapid Prototyping. FCCM Christopher Lavin, Marc Padilla, Jaren Lamprecht, Philip Lundrigan, Brent E. Nelson, Brad L. Hutchings
2011	B	`conf`	RapidSmith: Do-It-Yourself CAD Tools for Xilinx FPGAs. FPL Christopher Lavin, Marc Padilla, Jaren Lamprecht, Philip Lundrigan, Brent E. Nelson, Brad L. Hutchings
2011	B	`conf`	XDL-Based Module Generators for Rapid FPGA Design Implementation. FPL Subhrashankha Ghosh, Brent E. Nelson
2010	J	`jnl`	A Comparison Study on Implementing Optical Flow and Digital Communications on FPGAs and GPUs. ACM Trans. Reconfigurable Technol. Syst. John Bodily, Brent E. Nelson, Zhaoyi Wei, Dah-Jye Lee, Jeff Chase
2010	J	`jnl`	Hardware-Friendly Vision Algorithms for Embedded Obstacle Detection Applications. IEEE Trans. Circuits Syst. Video Technol. Zhaoyi Wei, Dah-Jye Lee, Brent E. Nelson, James K. Archibald
2010	B	`conf`	Increasing Design Productivity through Core Reuse, Meta-data Encapsulation, and Synthesis. FPL Adam Arnesen, Kevin Ellsworth, Derrick Gibelyou, Travis Haroldsen, Jared Havican, Marc Padilla, Brent E. Nelson, Michael Rice, Michael J. Wirthlin
2010	—	`conf`	Rapid prototyping tools for FPGA designs: RapidSmith. FPT Christopher Lavin, Marc Padilla, Philip Lundrigan, Brent E. Nelson, Brad L. Hutchings
2010	J	`jnl`	Two-frame structure from motion using optical flow probability distributions for unmanned air vehicle obstacle avoidance. Mach. Vis. Appl. Dah-Jye Lee, Paul C. Merrell, Zhaoyi Wei, Brent E. Nelson
2010	B	`conf`	Using Hard Macros to Reduce FPGA Compilation Time. FPL Christopher Lavin, Marc Padilla, Subhrashankha Ghosh, Brent E. Nelson, Brad L. Hutchings, Michael J. Wirthlin
2009	B	`ed.`	19th International Conference on Field Programmable Logic and Applications, FPL 2009, August 31 - September 2, 2009, Prague, Czech Republic FPL Martin Danek, Jiri Kadlec, Brent E. Nelson
2009	B	`conf`	Comparing fine-grained performance on the Ambric MPPA against an FPGA. FPL Brad L. Hutchings, Brent E. Nelson, Stephen West, Reed Curtis
2009	—	`conf`	FPGA Design Productivity - A Discussion of the State of the Art and a Research Agenda. ARC Brent E. Nelson
2009	J	`jnl`	Multi-frame structure from motion using optical flow probability distributions. Neurocomputing Dah-Jye Lee, Paul C. Merrell, Brent E. Nelson, Zhaoyi Wei
2009	Misc	`conf`	Optical Flow on the Ambric Massively Parallel Processor Array (MPPA). FCCM Brad L. Hutchings, Brent E. Nelson, Stephen West, Reed Curtis
2008	—	`conf`	Accurate Optical Flow Sensor for Obstacle Avoidance. ISVC (1) Zhaoyi Wei, Dah-Jye Lee, Brent E. Nelson, Kirt D. Lillywhite
2008	—	`conf`	Design Productivity for Configurable Computing. ERSA Brent E. Nelson, Michael J. Wirthlin, Brad L. Hutchings, Peter M. Athanas, Shawn A. Bohner
2008	J	`jnl`	Design, Debug, Deploy: The Creation of Configurable Computing Applications. J. Signal Process. Syst. Brent E. Nelson, Brad L. Hutchings, Michael J. Wirthlin
2008	J	`jnl`	FPGA-Based Embedded Motion Estimation Sensor. Int. J. Reconfigurable Comput. Zhaoyi Wei, Dah-Jye Lee, Brent E. Nelson, James K. Archibald, Barrett Edwards
2008	Misc	`conf`	Real-Time Optical Flow Calculations on FPGA and GPU Architectures: A Comparison Study. FCCM Jeff Chase, Brent E. Nelson, John Bodily, Zhaoyi Wei, Dah-Jye Lee
2008	B	`conf`	Real-time accurate optical flow-based motion sensor. ICPR Zhaoyi Wei, Dah-Jye Lee, Brent E. Nelson, James K. Archibald
2007	A	`conf`	A Fast and Accurate Tensor-based Optical Flow Algorithm Implemented in FPGA. WACV Zhaoyi Wei, Dah-Jye Lee, Brent E. Nelson, Michael Martineau
2007	—	`conf`	A Hardware-Friendly Adaptive Tensor Based Optical Flow Algorithm. ISVC (2) Zhaoyi Wei, Dah-Jye Lee, Brent E. Nelson
2007	J	`jnl`	FPGA-based Real-time Optical Flow Algorithm Design and Implementation. J. Multim. Zhaoyi Wei, Dah-Jye Lee, Brent E. Nelson
2006	—	`conf`	The Mythical CCM: In Search of Usable (and Resuable) FPGA-Based General Computing Machines. ASAP Brent E. Nelson
2005	B	`conf`	A Flexible Circuit-Switched NOC for FPGA-Based Systems. FPL Clint Hilton, Brent E. Nelson
2005	A	`conf`	Choice of base revisited: higher radices for FPGA-based floating-point computation (abstract only). FPGA Bryan Catanzaro, Brent E. Nelson
2005	Misc	`conf`	Higher Radix Floating-Point Representations for FPGA-Based Arithmetic. FCCM Bryan Catanzaro, Brent E. Nelson
2004	B	`conf`	A Parallel FFT Architecture for FPGAs. FPL Joseph M. Palmer, Brent E. Nelson
2004	J	`jnl`	GigaOp DSP on FPGA. J. VLSI Signal Process. Brad L. Hutchings, Brent E. Nelson
2004	B	`conf`	JHDLBits: The Merging of Two Worlds. FPL Alexandra Poetter, Jesse Hunter, Cameron D. Patterson, Peter M. Athanas, Brent E. Nelson, Neil Steiner
2003	Misc	`conf`	Reconfigurable Computing Application Frameworks. FCCM Anthony L. Slade, Brent E. Nelson, Brad L. Hutchings
2003	Misc	`conf`	Tradeoffs of Designing Floating-Point Division and Square Root on Virtex FPGAs. FCCM Xiaojun Wang, Brent E. Nelson
2002	—	`conf`	Debug methods for hybrid CPU/FPGA systems. FPT Eric Roesler, Brent E. Nelson
2002	B	`conf`	Novel Optimizations for Hardware Floating-Point Units in a Modern FPGA Architecture. FPL Eric Roesler, Brent E. Nelson
2001	Misc	`conf`	Gigaop DSP on FPGA. ICASSP Brad L. Hutchings, Brent E. Nelson
2001	Misc	`conf`	Instrumenting Bitstreams for Debugging FPGA Circuits. FCCM Paul S. Graham, Brent E. Nelson, Brad L. Hutchings
2001	J	`jnl`	Unifying simulation and execution in a design environment for FPGA systems. IEEE Trans. Very Large Scale Integr. Syst. Brad L. Hutchings, Brent E. Nelson
2001	B	`conf`	Using Design-Level Scan to Improve FPGA Design Observability and Controllability for Functional Verification. FPL Timothy Wheeler, Paul S. Graham, Brent E. Nelson, Brad L. Hutchings
2000	Misc	`conf`	A Reconfigurable Computing Architecture for Microsensors. FCCM Stephen M. Scalera, Mark Falco, Brent E. Nelson
2000	J	`jnl`	Designing and Debugging Custom Computing Applications. IEEE Des. Test Comput. Brad L. Hutchings, Brent E. Nelson, Michael J. Wirthlin
2000	Misc	`conf`	Improving the FPGA Design Process through Determining and Applying Logical-to-Physical Design Mappings. FCCM Paul S. Graham, Brad L. Hutchings, Brent E. Nelson
2000	A*	`conf`	Using general-purpose programming languages for FPGA design. DAC Brad L. Hutchings, Brent E. Nelson
1999	Misc	`conf`	A CAD Suite for High-Performance FPGA Design. FCCM Brad L. Hutchings, Peter Bellows, Joseph Hawkins, K. Scott Hemmert, Brent E. Nelson, Mike Rytting
1999	J	`jnl`	Error control coding in software radios: an FPGA approach. IEEE Wirel. Commun. Gregory C. Ahlquist, Michael Rice, Brent E. Nelson
1999	B	`conf`	Optimal Finite Field Multipliers for FPGAs. FPL Gregory C. Ahlquist, Brent E. Nelson, Michael Rice
1999	B	`conf`	Reconfigurable Processors for High-Performance, Embedded Digital Signal Processing. FPL Paul S. Graham, Brent E. Nelson
1998	A	`conf`	FPGA-Based Sonar Processing. FPGA Paul S. Graham, Brent E. Nelson
1998	Misc	`conf`	Frequency-Domain Sonar Processing in FPGAs and DSPs. FCCM Paul S. Graham, Brent E. Nelson
1996	Misc	`conf`	Genetic algorithms in software and in hardware-a performance analysis of workstation and custom computing machine implementations. FCCM Paul S. Graham, Brent E. Nelson
1996	J	`jnl`	Locality as a Visualization Tool. IEEE Trans. Computers Knuth Stener Grimsrud, James K. Archibald, Richard L. Frost, Brent E. Nelson
1996	B	`conf`	The Inaccuracy of Trace-Driven Simulation Using Incomplete Mulitprogramming Trace Data. MASCOTS J. Kelly Flanagan, Brent E. Nelson, James K. Archibald, Gregory D. Thompson
1996	B	`conf`	Transaction Processing Workloads - A Comparison to the SPEC Benchmarks Using Memory Hierarchy Performance Studies. MASCOTS Brent E. Nelson, Gregory D. Thompson, J. Kelly Flanagan
1995	B	`conf`	A Hardware Genetic Algorithm for the Travelling Salesman Problem on SPLASH 2. FPL Paul S. Graham, Brent E. Nelson
1994	—	`conf`	On the Accuracy of Memory Reference Models. Computer Performance Evaluation Knuth Stener Grimsrud, James K. Archibald, Richard L. Frost, Brent E. Nelson
1993	J	`jnl`	BACH: a hardware monitor for tracing microprocessor-based systems. Microprocess. Microsystems Knuth Stener Grimsrud, James K. Archibald, M. Ripley, J. Kelly Flanagan, Brent E. Nelson
1993	J	`jnl`	Evaluating Performance of Prefetching Second Level Caches. SIGMETRICS Perform. Evaluation Rev. Robert B. Smith, James K. Archibald, Brent E. Nelson
1993	B	`conf`	Incomplete Trace Data and Trace Driven Simulation. MASCOTS J. Kelly Flanagan, Brent E. Nelson, James K. Archibald, Knuth Stener Grimsrud
1993	J	`jnl`	Multiple Prefetch Adaptive Disk Caching. IEEE Trans. Knowl. Data Eng. Knuth Stener Grimsrud, James K. Archibald, Brent E. Nelson
1991	—	`conf`	Performance analysis of inclusion effects in multi-level multiprocessor caches. SPDP Brent E. Nelson, James K. Archibald, J. Kelly Flanagan
1989	Misc	`conf`	Vector quantization codebook generation using simulated annealing. ICASSP J. Kelly Flanagan, Darryl Morrell, Richard L. Frost, Christopher J. Read, Brent E. Nelson
1988	C	`conf`	Processor design using path programmable logic. ICCD J. Kelly Flanagan, Brent E. Nelson
1987	Misc	`conf`	A multiprogrammed parallel architecture for digital signal processing. ICASSP Tao Li, Brent E. Nelson, J. Kelly Flanagan, Christopher J. Read
1986	Misc	`conf`	A bit-serial VLSI vector quantizer. ICASSP Brent E. Nelson, Christopher J. Read
1984	A*	`conf`	The structure and operation of a relational database system in a cell-oriented integrated circuit design system. DAC Lee A. Hollaar, Brent E. Nelson, Tony M. Carter, Raymond A. Lorie
1984	—	`conf`	Transforming an Ada Program Unit to Silicon and Testing It in an Ada Environment. COMPCON Tony M. Carter, Alan L. Davis, Alan B. Hayes, Gary Lindstrom, Dan Klass, Mike P. Maloney, Brent E. Nelson, Elliott I. Organick, Kent F. Smith
1984	J	`jnl`	Transforming an Ada Program Unit to Silicon and Verifying Its Behavior in an Ada Environment: A first Experiment. IEEE Softw. Elliott I. Organick, Tony M. Carter, Mike P. Maloney, Alan L. Davis, Alan B. Hayes, Dan Klass, Gary Lindstrom, Brent E. Nelson, Kent F. Smith