Brandon Noia

20 papers A 3B 1C 1Misc 1Journal 8Unranked 4
YearRankTypeTitle / Venue / Authors
2015 J jnl
Scan Test of Die Logic in 3-D ICs Using TSV Probing.
IEEE Trans. Very Large Scale Integr. Syst.
Brandon Noia, Shreepad Panth, Krishnendu Chakrabarty, Sung Kyu Lim
2014 — book
Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs.
Brandon Noia, Krishnendu Chakrabarty
2014 — —
Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs.
Brandon Noia
2014 J jnl
Retiming for Delay Recovery After DfT Insertion on Interdie Paths in 3-D ICs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Brandon Noia, Krishnendu Chakrabarty
2014 J jnl
Test and Design-for-Testability Solutions for 3D Integrated Circuits.
Inf. Media Technol.
Krishnendu Chakrabarty, Mukesh Agrawal, Sergej Deutsch, Brandon Noia, Ran Wang, Fangming Ye
2014 J jnl
Test and Design-for-Testability Solutions for 3D Integrated Circuits.
IPSJ Trans. Syst. LSI Des. Methodol.
Krishnendu Chakrabarty, Mukesh Agrawal, Sergej Deutsch, Brandon Noia, Ran Wang, Fangming Ye
2013 — conf
Face-to-face bus design with built-in self-test in 3D ICs.
3DIC
Zhenqian Zhang, Brandon Noia, Krishnendu Chakrabarty, Paul D. Franzon
2013 Misc conf
Post-DfT-insertion retiming for delay recovery on inter-die paths in 3D ICs.
VTS
Brandon Noia, Krishnendu Chakrabarty
2013 J jnl
Pre-Bond Probing of Through-Silicon Vias in 3-D Stacked ICs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Brandon Noia, Krishnendu Chakrabarty
2012 J jnl
Optimization Methods for Post-Bond Testing of 3D Stacked ICs.
J. Electron. Test.
Brandon Noia, Krishnendu Chakrabarty, Erik Jan Marinissen
2012 A conf
Scan test of die logic in 3D ICs using TSV probing.
ITC
Brandon Noia, Shreepad Panth, Krishnendu Chakrabarty, Sung Kyu Lim
2011 — conf
Identification of Defective TSVs in Pre-Bond Testing of 3D ICs.
Asian Test Symposium
Brandon Noia, Krishnendu Chakrabarty
2011 A conf
Pre-bond probing of TSVs in 3D stacked ICs.
ITC
Brandon Noia, Krishnendu Chakrabarty
2011 — conf
Pre-bond testing of die logic and TSVs in high performance 3D-SICs.
3DIC
Brandon Noia, Krishnendu Chakrabarty
2011 J jnl
Test-Architecture Optimization and Test Scheduling for TSV-Based 3-D Stacked ICs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Brandon Noia, Krishnendu Chakrabarty, Sandeep Kumar Goel, Erik Jan Marinissen, Jouke Verbree
2011 J jnl
Test-wrapper optimisation for embedded cores in through-silicon via-based three-dimensional system on chips.
IET Comput. Digit. Tech.
Brandon Noia, Krishnendu Chakrabarty
2011 — conf
Testing and Design-for-Testability Techniques for 3D Integrated Circuits.
Asian Test Symposium
Brandon Noia, Krishnendu Chakrabarty
2010 A conf
Optimization methods for post-bond die-internal/external testing in 3D stacked ICs.
ITC
Brandon Noia, Krishnendu Chakrabarty, Erik Jan Marinissen
2010 B conf
Test-architecture optimization for TSV-based 3D stacked ICs.
ETS
Brandon Noia, Sandeep Kumar Goel, Krishnendu Chakrabarty, Erik Jan Marinissen, Jouke Verbree
2009 C conf
Test-wrapper optimization for embedded cores in TSV-based three-dimensional SOCs.
ICCD
Brandon Noia, Krishnendu Chakrabarty, Yuan Xie