Bradley S. Carlson

21 papers A* 1C 4Journal 9Unranked 7
YearRankTypeTitle / Venue / Authors
2001 — conf
Principles vs. Practices in Undergraduate Microelectronic Systems Education.
MSE
Bradley S. Carlson
2000 — conf
Power estimation for a submicron CMOS inverter driving a CRC interconnect load.
ACM Great Lakes Symposium on VLSI
Hung-Jung Chen, Bradley S. Carlson
1999 J jnl
Transistor Chaining in Static CMOS Functional Cells of Arbitrary Planar Topology.
Discret. Appl. Math.
Bradley S. Carlson, C. Y. Roger Chen, Dikran S. Meliksetian
1998 — conf
Parallel implementation of a unified approach to image focus and defocus analysis on the Parallel Virtual Machine.
Visual Information Processing
Yen-Fu Liu, Nai-Wei Lo, Murali Subbarao, Bradley S. Carlson
1997 — conf
A VLSI circuit design course for practitioners and researchers.
MSE
Bradley S. Carlson
1997 C conf
Critical Voltage Transition Logic: An Ultrafast CMOS Logic Family.
ICCD
Zhang Zhu, Bradley S. Carlson
1997 J jnl
Fault Tolerant Algorithms for Broadcasting on the Star Graph Network.
IEEE Trans. Computers
Nai-Wei Lo, Bradley S. Carlson, D. L. Tao
1997 J jnl
Parallel logic simulation on a network of workstations using parallel virtual machine.
ACM Trans. Design Autom. Electr. Syst.
Maciek Kormicki, Ausif Mahmood, Bradley S. Carlson
1996 J jnl
A Unified Algorithm for the Estimation and Scheduling of Data Flow Graphs.
J. Circuits Syst. Comput.
Yuan Hu, Bradley S. Carlson
1996 — conf
Parallel logic simulation on a network of workstations using PVM.
SPDP
Maciek Kormicki, Ausif Mahmood, Bradley S. Carlson
1996 — conf
Transistor Chaining in CMOS Leaf Cells of Planar Topology.
Great Lakes Symposium on VLSI
Bradley S. Carlson, C. Y. Roger Chen, Dikran S. Meliksetian
1995 J jnl
A preprocessor for improving channel routing hierarchical pin permutation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
C. Y. Roger Chen, Cliff Yungchin Hou, Bradley S. Carlson
1995 J jnl
Delay optimization of digital CMOS VLSI circuits by transistor reordering.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Bradley S. Carlson, Suh-Juch Lee
1995 J jnl
Dual Eulerian Properties of Plane Multigraphs.
SIAM J. Discret. Math.
Bradley S. Carlson, C. Y. Roger Chen, Dikran S. Meliksetian
1995 J jnl
LILA: layout generation for iterative logic arrays.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Qinghong Wu, C. Y. Roger Chen, Bradley S. Carlson
1995 — conf
Synthesis of SEU-tolerant ASICs using concurrent error correction.
Great Lakes Symposium on VLSI
Harry Hollander, Bradley S. Carlson, Toby D. Bennett
1994 C conf
A Unified Algorithm for Estimation and Scheduling in Data Path Synthesis.
ISCAS
Yuan Hu, Bradley S. Carlson
1994 C conf
Improved Lower Bounds for the Scheduling Optimization Problem.
ISCAS
Yuan Hu, Bradley S. Carlson
1993 C conf
Lower Bounds on the Iteration Time and the Number of Resources for Functional Pipelined Data Flow Graphs.
ICCD
Yuan Hu, Ahmed Ghouse, Bradley S. Carlson
1993 A* conf
Performance Enhancement of CMOS VLSI Circuits by Transistor Reordering.
DAC
Bradley S. Carlson, C. Y. Roger Chen
1991 J jnl
Optimal cell generation for dual independent layout styles.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Bradley S. Carlson, C. Y. Roger Chen, Uminder Singh