Bradley A. Bloechel

11 papers Journal 8Unranked 3

Year	Rank	Type	Title / Venue / Authors
2005	—	`conf`	A 10Mbit, 15GBytes/sec bandwidth 1T DRAM chip with planar MOS storage capacitor in an unmodified 150nm logic process for high-density on-chip memory applications. ESSCIRC Dinesh Somasekhar, Shih-Lien Lu, Bradley A. Bloechel, Greg Dermer, Konrad Lai, Sjeljar Borkar, Vivek De
2005	J	`jnl`	A 233-MHz 80%-87% efficient four-phase DC-DC converter utilizing air-core inductors on package. IEEE J. Solid State Circuits Peter Hazucha, Gerhard Schrom, Jaehong Hahn, Bradley A. Bloechel, Paul Hack, Gregory E. Dermer, Siva G. Narendra, Donald S. Gardner, Tanay Karnik, Vivek De, Shekhar Borkar
2005	J	`jnl`	Area-efficient linear regulator with ultra-fast load regulation. IEEE J. Solid State Circuits Peter Hazucha, Tanay Karnik, Bradley A. Bloechel, Colleen Parsons, David Finan, Shekhar Borkar
2004	J	`jnl`	Measurements and analysis of SER-tolerant latch in a 90-nm dual-V IEEE J. Solid State Circuits Peter Hazucha, Tanay Karnik, Steven Walstra, Bradley A. Bloechel, James W. Tschanz, Jose Maiz, Krishnamurthy Soumyanath, Gregory E. Dermer, Siva G. Narendra, Vivek De, Shekhar Borkar
2003	—	`conf`	17GHz and 24GHz LNA designs based on extended-S-parameter with microstrip-on-die in 0.18μm logic CMOS technology. ESSCIRC Luiz M. Franca-Neto, Bradley A. Bloechel, Krishnamurthy Soumyanath
2003	J	`jnl`	A TCP offload accelerator for 10 Gb/s Ethernet in 90-nm CMOS. IEEE J. Solid State Circuits Yatin Vasant Hoskote, Bradley A. Bloechel, Gregory E. Dermer, Vasantha Erraguntla, David Finan, Jason Howard, Dan Klowden, Siva G. Narendra, Greg Ruhl, James W. Tschanz, Sriram R. Vangal, Venkat Veeramachaneni, Howard Wilson, Jianping Xu, Nitin Borkar
2003	J	`jnl`	Dynamic sleep transistor and body bias for active leakage power control of microprocessors. IEEE J. Solid State Circuits James W. Tschanz, Siva G. Narendra, Yibin Ye, Bradley A. Bloechel, Shekhar Borkar, Vivek De
2003	J	`jnl`	Forward body bias for microprocessors in 130-nm technology generation and beyond. IEEE J. Solid State Circuits Siva G. Narendra, Ali Keshavarzi, Bradley A. Bloechel, Shekhar Borkar, Vivek De
2003	—	`conf`	Measurements and analysis of SER tolerant latch in a 90 nm dual-Vt CMOS process. CICC Peter Hazucha, Tanay Kamik, Steven Walstra, Bradley A. Bloechel, James W. Tschanz, Jose Maiz, Krishnamurthy Soumyanath, Greg Dermer, Siva G. Narendra, Vivek De, Shekhar Borkar
2002	J	`jnl`	5-GHz 32-bit integer execution core in 130-nm dual-V IEEE J. Solid State Circuits Sriram R. Vangal, Mark A. Anders, Nitin Borkar, Erik Seligman, Venkatesh Govindarajulu, Vasantha Erraguntla, Howard Wilson, Amaresh Pangal, Venkat Veeramachaneni, James W. Tschanz, Yibin Ye, Dinesh Somasekhar, Bradley A. Bloechel, Gregory E. Dermer, Ram K. Krishnamurthy, Krishnamurthy Soumyanath, Sanu Mathew, Siva G. Narendra, Mircea R. Stan, Scott Thompson, Vivek De, Shekhar Borkar
1999	J	`jnl`	Accurate on-chip interconnect evaluation: a time-domain technique. IEEE J. Solid State Circuits Krishnamurthy Soumyanath, Shekhar Borkar, Chunyan Zhou, Bradley A. Bloechel