Brad L. Hutchings

81 papers A* 2A 9B 18Misc 20Journal 16Unranked 16

Year	Rank	Type	Title / Venue / Authors
2023	B	`conf`	Improving the Reliability of FPGA CRO PUFs. FPL Hayden Cook, Zephram Tripp, Brad L. Hutchings, Jeffrey Goeders
2022	J	`jnl`	Approaches for FPGA Design Assurance. ACM Trans. Reconfigurable Technol. Syst. Eli Cahill, Brad L. Hutchings, Jeffrey Goeders
2022	—	`conf`	Cloning the Unclonable: Physically Cloning an FPGA Ring-Oscillator PUF. FPT Hayden Cook, Jonathan Thompson, Zephram Tripp, Brad L. Hutchings, Jeffrey Goeders
2022	J	`jnl`	Inducing Non-uniform FPGA Aging Using Configuration-based Short Circuits. ACM Trans. Reconfigurable Technol. Syst. Hayden Cook, Jacob Arscott, Brent George, Tanner Gaskin, Jeffrey Goeders, Brad L. Hutchings
2020	B	`conf`	Using Novel Configuration Techniques for Accelerated FPGA Aging. FPL Tanner Gaskin, Hayden Cook, Wesley Stirk, Robert Lucas, Jeffrey Goeders, Brad L. Hutchings
2019	B	`conf`	Preallocating Resources for Distributed Memory Based FPGA Debug. FPL Robert Hale, Brad L. Hutchings
2018	Misc	`conf`	Demand Driven Assembly of FPGA Configurations Using Partial Reconfiguration, Ubuntu Linux, and PYNQ. FCCM Jeffrey Goeders, Tanner Gaskin, Brad L. Hutchings
2018	—	`conf`	Distributed-Memory Based FPGA Debug: Design Timing Impact. FPT Robert Hale, Brad L. Hutchings
2018	B	`conf`	Enabling Low Impact, Rapid Debug for Highly Utilized FPGA Designs. FPL Robert Hale, Brad L. Hutchings
2018	J	`jnl`	Enhancing debug observability for HLS-based FPGA circuits through source-to-source compilation. J. Parallel Distributed Comput. Joshua S. Monson, Brad L. Hutchings
2018	—	`conf`	Using Physical and Functional Comparisons to Assure 3rd-Party IP for Modern FPGAs. IVSW Adam Hastings, Sean Jensen, Jeffrey Goeders, Brad L. Hutchings
2017	B	`conf`	Rapid implementation of a partially reconfigurable video system with PYNQ. FPL Brad L. Hutchings, Michael J. Wirthlin
2016	—	`conf`	Packing a modern Xilinx FPGA using RapidSmith. ReConFig Travis Haroldsen, Brent E. Nelson, Brad L. Hutchings
2015	A	`conf`	RapidSmith 2: A Framework for BEL-level CAD Exploration on Xilinx FPGAs. FPGA Travis Haroldsen, Brent E. Nelson, Brad L. Hutchings
2015	A	`conf`	Using Source-Level Transformations to Improve High-Level Synthesis Debug and Validation on FPGAs. FPGA Joshua S. Monson, Brad L. Hutchings
2015	—	`conf`	Using shadow pointers to trace C pointer values in FPGA circuits. ReConFig Joshua S. Monson, Brad L. Hutchings
2015	—	`conf`	Using source-to-source compilation to instrument circuits for debug with High Level Synthesis. FPT Joshua S. Monson, Brad L. Hutchings
2014	A	`conf`	A power side-channel-based digital to analog converterfor Xilinx FPGAs. FPGA Brad L. Hutchings, Joshua S. Monson, Danny Savory, Jared Keeley
2014	B	`conf`	New approaches for in-system debug of behaviorally-synthesized FPGA circuits. FPL Joshua S. Monson, Brad L. Hutchings
2014	Misc	`conf`	Rapid Post-Map Insertion of Embedded Logic Analyzers for Xilinx FPGAs. FCCM Brad L. Hutchings, Jared Keeley
2013	B	`conf`	Impact of hard macro size on FPGA clock rate and place/route time. FPL Christopher Lavin, Brent E. Nelson, Brad L. Hutchings
2013	—	`conf`	Implementing high-performance, low-power FPGA-based optical flow accelerators in C. ASAP Joshua S. Monson, Michael J. Wirthlin, Brad L. Hutchings
2013	—	`conf`	Improving clock-rate of hard-macro designs. FPT Christopher Lavin, Brent E. Nelson, Brad L. Hutchings
2013	—	`conf`	Optimization techniques for a high level synthesis implementation of the Sobel filter. ReConFig Joshua S. Monson, Michael J. Wirthlin, Brad L. Hutchings
2013	A	`ed.`	The 2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA '13, Monterey, CA, USA, February 11-13, 2013 FPGA Brad L. Hutchings, Vaughn Betz
2012	J	`jnl`	A Fault Injection Analysis of Linux Operating on an FPGA-Embedded Platform. Int. J. Reconfigurable Comput. Joshua S. Monson, Michael J. Wirthlin, Brad L. Hutchings
2012	A	`ed.`	Proceedings of the ACM/SIGDA 20th International Symposium on Field Programmable Gate Arrays, FPGA 2012, Monterey, California, USA, February 22-24, 2012 FPGA Katherine Compton, Brad L. Hutchings
2012	B	`conf`	Profiling FPGA floor-planning effects on timing closure. FPL Jaren Lamprecht, Brad L. Hutchings
2012	J	`jnl`	The NII Shonan Configurable Computing Workshop (NII Shonan Meeting 2012-11). NII Shonan Meet. Rep. Peter M. Athanas, Brad L. Hutchings, Kentaro Sano
2011	Misc	`conf`	FPGA Communication Framework. FCCM Peter Lieber, Brad L. Hutchings
2011	Misc	`conf`	HMFlow: Accelerating FPGA Compilation with Hard Macros for Rapid Prototyping. FCCM Christopher Lavin, Marc Padilla, Jaren Lamprecht, Philip Lundrigan, Brent E. Nelson, Brad L. Hutchings
2011	B	`conf`	RapidSmith: Do-It-Yourself CAD Tools for Xilinx FPGAs. FPL Christopher Lavin, Marc Padilla, Jaren Lamprecht, Philip Lundrigan, Brent E. Nelson, Brad L. Hutchings
2010	—	`conf`	Fault Injection Results of Linux Operating on an FPGA Embedded Platform. ReConFig Joshua S. Monson, Michael J. Wirthlin, Brad L. Hutchings
2010	—	`conf`	Rapid prototyping tools for FPGA designs: RapidSmith. FPT Christopher Lavin, Marc Padilla, Philip Lundrigan, Brent E. Nelson, Brad L. Hutchings
2010	B	`conf`	Using Hard Macros to Reduce FPGA Compilation Time. FPL Christopher Lavin, Marc Padilla, Subhrashankha Ghosh, Brent E. Nelson, Brad L. Hutchings, Michael J. Wirthlin
2009	B	`conf`	Comparing fine-grained performance on the Ambric MPPA against an FPGA. FPL Brad L. Hutchings, Brent E. Nelson, Stephen West, Reed Curtis
2009	Misc	`conf`	Optical Flow on the Ambric Massively Parallel Processor Array (MPPA). FCCM Brad L. Hutchings, Brent E. Nelson, Stephen West, Reed Curtis
2008	—	`conf`	Design Productivity for Configurable Computing. ERSA Brent E. Nelson, Michael J. Wirthlin, Brad L. Hutchings, Peter M. Athanas, Shawn A. Bohner
2008	J	`jnl`	Design, Debug, Deploy: The Creation of Configurable Computing Applications. J. Signal Process. Syst. Brent E. Nelson, Brad L. Hutchings, Michael J. Wirthlin
2004	J	`jnl`	GigaOp DSP on FPGA. J. VLSI Signal Process. Brad L. Hutchings, Brent E. Nelson
2004	A	`conf`	What is the right model for programming and using modern FPGAs? FPGA André DeHon, Brad L. Hutchings, Daryl Rudusky, James Hwang, Nikhil, Salil Raje, Adrian Stoica
2003	—	`conf`	Adaptive computing: what can it do, where can it go? ASP-DAC Robert Reuss, Jose L. Muñoz, Toshiaki Miyazaki, Nader Bagherzadeh, Prith Banerjee, Brad L. Hutchings, Brian Schott
2003	—	`conf`	Issues in debugging highly parallel FPGA-based applications derived from source code. ASP-DAC K. Scott Hemmert, Brad L. Hutchings
2003	Misc	`conf`	Reconfigurable Computing Application Frameworks. FCCM Anthony L. Slade, Brent E. Nelson, Brad L. Hutchings
2003	Misc	`conf`	Simulation and Synthesis of CSP-based Interprocess Communication. FCCM Preston A. Jackson, Brad L. Hutchings, Justin L. Tripp
2003	Misc	`conf`	Source Level Debugger for the Sea Cucumber Synthesizing Compiler. FCCM K. Scott Hemmert, Justin L. Tripp, Brad L. Hutchings, Preston A. Jackson
2002	J	`jnl`	Algorithms for Coloring Quadtrees. Algorithmica David Eppstein, Marshall W. Bern, Brad L. Hutchings
2002	Misc	`conf`	Assisting Network Intrusion Detection with Reconfigurable Hardware. FCCM Brad L. Hutchings, R. Franklin, D. Carver
2002	B	`conf`	Multitasking Hardware on the SLAAC1-V Reconfigurable Computing System. FPL Wesley J. Landaker, Michael J. Wirthlin, Brad L. Hutchings
2002	B	`conf`	Sea Cucumber: A Synthesizing Compiler for FPGAs. FPL Justin L. Tripp, Preston A. Jackson, Brad L. Hutchings
2001	Misc	`conf`	An Application-Specific Compiler for High-Speed Binary Image Morphology. FCCM K. Scott Hemmert, Brad L. Hutchings, Anshul Malvi
2001	J	`jnl`	Designing Run-Time Reconfigurable Systems with JHDL. J. VLSI Signal Process. Peter Bellows, Brad L. Hutchings
2001	Misc	`conf`	Gigaop DSP on FPGA. ICASSP Brad L. Hutchings, Brent E. Nelson
2001	Misc	`conf`	Instrumenting Bitstreams for Debugging FPGA Circuits. FCCM Paul S. Graham, Brent E. Nelson, Brad L. Hutchings
2001	B	`conf`	Synthesizing RTL Hardware from Java Byte Codes. FPL Michael J. Wirthlin, Brad L. Hutchings, Carl D. Worth
2001	J	`jnl`	Unifying simulation and execution in a design environment for FPGA systems. IEEE Trans. Very Large Scale Integr. Syst. Brad L. Hutchings, Brent E. Nelson
2001	B	`conf`	Using Design-Level Scan to Improve FPGA Design Observability and Controllability for Functional Verification. FPL Timothy Wheeler, Paul S. Graham, Brent E. Nelson, Brad L. Hutchings
2000	J	`jnl`	Designing and Debugging Custom Computing Applications. IEEE Des. Test Comput. Brad L. Hutchings, Brent E. Nelson, Michael J. Wirthlin
2000	Misc	`conf`	Improving the FPGA Design Process through Determining and Applying Logical-to-Physical Design Mappings. FCCM Paul S. Graham, Brad L. Hutchings, Brent E. Nelson
2000	A*	`conf`	Using general-purpose programming languages for FPGA design. DAC Brad L. Hutchings, Brent E. Nelson
1999	Misc	`conf`	A CAD Suite for High-Performance FPGA Design. FCCM Brad L. Hutchings, Peter Bellows, Joseph Hawkins, K. Scott Hemmert, Brent E. Nelson, Mike Rytting
1999	A	`conf`	A Reconfigurable Arithmetic Array for Multimedia Application. FPGA Alan Marshall, Tony Stansfield, Igor Kostarnov, Jean Vuillemin, Brad L. Hutchings
1999	J	`jnl`	Algorithms for Coloring Quadtrees CoRR David Eppstein, Marshall W. Bern, Brad L. Hutchings
1998	J	`jnl`	Improving functional density using run-time circuit reconfiguration [FPGAs]. IEEE Trans. Very Large Scale Integr. Syst. Michael J. Wirthlin, Brad L. Hutchings
1998	Misc	`conf`	JHDL - An HDL for Reconfigurable Systems. FCCM Peter Bellows, Brad L. Hutchings
1998	J	`jnl`	The flexibility of configurable computing. IEEE Signal Process. Mag. John D. Villasenor, Brad L. Hutchings
1997	—	`conf`	ASICs, Processors, and Configurable Computing. HICSS (1) Brad L. Hutchings
1997	Misc	`conf`	Automated target recognition on SPLASH 2. FCCM Michael Rencher, Brad L. Hutchings
1997	B	`conf`	Exploiting reconfigurability through domain-specific systems. FPL Brad L. Hutchings
1997	A	`conf`	Improving Functional Density Through Run-Time Constant Propagation. FPGA Michael J. Wirthlin, Brad L. Hutchings
1996	Misc	`conf`	Mixing fixed and reconfigurable logic for array processing. FCCM Pieter J. Bakkes, Jan J. Du Plessis, Brad L. Hutchings
1996	J	`jnl`	Run-Time Reconfiguration: A method for enhancing the functional density of SRAM-based FPGAs. J. VLSI Signal Process. James G. Eldredge, Brad L. Hutchings
1996	A	`conf`	Sequencing Run-Time Reconfigured Hardware with Software. FPGA Michael J. Wirthlin, Brad L. Hutchings
1996	Misc	`conf`	Supporting FPGA microprocessors through retargetable software tools. FCCM David A. Clark, Brad L. Hutchings
1995	Misc	`conf`	A dynamic instruction set computer. FCCM Michael J. Wirthlin, Brad L. Hutchings
1995	B	`conf`	An Assessment of the Suitability of FPGA-Based Systems for Use in Digital Signal Processing. FPL Russell J. Petersen, Brad L. Hutchings
1995	Misc	`conf`	Design methodologies for partially reconfigured systems. FCCM James D. Hadley, Brad L. Hutchings
1995	B	`conf`	Implementation Approaches for Reconfigurable Logic Applications. FPL Brad L. Hutchings, Michael J. Wirthlin
1994	—	`conf`	High-Speed Circuit Design: CAD Tools and Computational Challenges. HICSS (1) Brad L. Hutchings, Tony M. Carter
1994	A*	`conf`	Multiple-Layer Cross-Field Ultrasonic Tactile Sensor. ICRA Brad L. Hutchings, A. R. Grahn, Russell J. Petersen
1989	J	`jnl`	VLSI design and implementation of a real-time image segmentation processor. Mach. Vis. Appl. Bir Bhanu, Brad L. Hutchings, Kent F. Smith