Bozhi Yin - RankMe

14 papers C 2Journal 2Unranked 9

Year	Rank	Type	Title / Venue / Authors
2024	C	`conf`	A 24.6-29.6GHz Hybrid Sub-Sampling PLL with Tri-State Integral Path Achieving 44fs Jitter and -254.8dB FOM in 28nm CMOS. ISCAS Zhongkai Wang, Minsoo Choi, Paul Kwon, Zhaokai Liu, Bozhi Yin, Kyoungtae Lee, Kwanseo Park, Ayan Biswas, Jaeduk Han, Sijun Du, Elad Alon
2024	—	`—`	Cryogenic Optical Link: Device, Circuit, and System Bozhi Yin
2022	—	`conf`	A 200Gb/s PAM-4 Transmitter with Hybrid Sub-Sampling PLL in 28nm CMOS Technology. VLSI Technology and Circuits Zhongkai Wang, Minsoo Choi, Paul Kwon, Kyoungtae Lee, Bozhi Yin, Zhaokai Liu, Kwanseo Park, Ayan Biswas, Jaeduk Han, Sijun Du, Elad Alon
2022	C	`conf`	A Ring-Oscillator Sub-Sampling PLL With Hybrid Loop Using Generator-Based Design Flow. ISCAS Zhongkai Wang, Minsoo Choi, John Charles Wright, Kyoungtae Lee, Zhaokai Liu, Bozhi Yin, Jaeduk Han, Sijun Du, Elad Alon
2021	—	`conf`	Cryo-Compatible, Silicon Spoked-Ring Modulator in a 45nm CMOS Platform for 4K-to-Room-Temperature Optical Links. OFC Hayk Gevorgyan, Anatol Khilo, Derek Van Orden, Deniz Onural, Bozhi Yin, Mark T. Wade, Vladimir Marko Stojanovic, Milos A. Popovic
2021	—	`conf`	Electronic-Photonic Cryogenic Egress Link. ESSCIRC Bozhi Yin, Hayk Gevorgyan, Deniz Onural, Anatol Khilo, Milos A. Popovic, Vladimir Marko Stojanovic
2021	—	`conf`	Electronic-Photonic Cryogenic Egress Link. ESSDERC Bozhi Yin, Hayk Gevorgyan, Deniz Onural, Anatol Khilo, Milos A. Popovic, Vladimir Marko Stojanovic
2020	J	`jnl`	A 50-Gb/s PAM4 Si-Photonic Transmitter With Digital-Assisted Distributed Driver and Integrated CDR in 40-nm CMOS. IEEE J. Solid State Circuits Qiwen Liao, Nan Qi, Miaofeng Li, Shang Hu, Jian He, Bozhi Yin, Jingbo Shi, Jian Liu, Patrick Yin Chiang, Xi Xiao, Nanjian Wu
2020	J	`jnl`	A Laser-Forwarded Coherent Transceiver in 45-nm SOI CMOS Using Monolithic Microring Resonators. IEEE J. Solid State Circuits Nandish Mehta, Sen Lin, Bozhi Yin, Sajjad Moazeni, Vladimir Stojanovic
2019	—	`conf`	A 50Gb/s PAM-4 Retimer-CDR + VCSEL Driver with Asymmetric Pulsed Pre-Emphasis Integrated into a Single CMOS Die. OFC Shang Hu, Tingyu Yao, Bozhi Yin, Chunyu Song, Lei Zhao, Juncheng Wang, Lei Wang, Rui Bai, Xin Wang, Tao Xia, Yi Peng, Binbin Yao, Yuan Li, Xuefeng Chen, Quan Pan, Nan Qi, Patrick Yin Chiang
2019	—	`conf`	A Laser-forwarded Coherent 10Gb/s BPSK Transceiver using Monolithic Microring Resonators in 45nm SOI CMOS. VLSI Circuits Nandish Mehta, Sen Lin, Bozhi Yin, Sajjad Moazeni, Vladimir Stojanovic
2018	—	`conf`	A 50Gb/s-PAM4 CDR with On-Chip Eye Opening Monitor for Reference-Level and Clock-Sampling Adaptation. OFC Chang Liu, Bozhi Yin, Tingyu Yao, Nan Qi, Dan Li, Jingbo Shi, Juncheng Wang, Hu Shang, Rui Bai, Patrick Yin Chiang
2018	—	`conf`	A Fully-Integrated 25Gb/s Low-Noise TIA+CDR Optical Receiver designed in 40nm-CMOS. A-SSCC Juncheng Wang, Xuefeng Chen, Shang Hu, Yaxin Cai, Rui Bai, Xin Wang, Yuanxi Zhang, Shenglong Zhuo, Chang Liu, Bozhi Yin, Jianxu Ma, Hao Yan, Jiangao Xuan, Milton Lu, Tao Xia, Nan Qi, Patrick Yin Chiang
2017	—	`conf`	A 51Gb/s, 320mW, PAM4 CDR with baud-rate sampling for high-speed optical interconnects. A-SSCC Nan Qi, Yuhang Kang, Qipeng Lin, Jianxu Ma, Jingbo Shi, Bozhi Yin, Chang Liu, Rui Bai, Shang Hu, Juncheng Wang, Jiangbing Du, Lin Ma, Zuyuan He, Ming Liu, Feng Zhang, Patrick Yin Chiang