Bongjin Kim

79 papers A 3C 7Journal 32Unranked 37
YearRankTypeTitle / Venue / Authors
2026 — conf
10.8 COBI: A Degree-of-56 Column-Bipartite Densely Connected Digital Ising Chip with 8b Spin Coefficients.
ISSCC
Yihao Wu, Jooyoung Bae, Seunghun Shin, Bongjin Kim
2025 J jnl
A Graph-Based Accelerator of Retinex Model With Bit-Serial Computing for Image Enhancements.
IEEE Trans. Circuits Syst. I Regul. Pap.
Zhengzhe Wei, Junjie Mu, Yuanjin Zheng, Tony Tae-Hyoung Kim, Bongjin Kim
2024 — conf
15.5 LISA: A 576×4 All-in-One Replica-Spins Continuous-Time Latch-Based Ising Computer Using Massively-Parallel Random-Number Generations and Replica Equalizations.
ISSCC
Jooyoung Bae, Jahyun Koo, Chaeyun Shim, Bongjin Kim
2024 — conf
15.6 e-Chimera: A Scalable SRAM-Based Ising Macro with Enhanced-Chimera Topology for Solving Combinatorial Optimization Problems Within Memory.
ISSCC
Jooyoung Bae, Chaeyun Shim, Bongjin Kim
2024 — conf
30.3 VIP-Sat: A Boolean Satisfiability Solver Featuring 5×12 Variable In-Memory Processing Elements with 98% Solvability for 50-Variables 218-Clauses 3-SAT Problems.
ISSCC
Chaeyun Shim, Jooyoung Bae, Bongjin Kim
2024 J jnl
A 26-Gb/s Framed-Pulsewidth Modulation Transceiver for Extended Reach Optical Links.
IEEE J. Solid State Circuits
Woohyun Kwon, Hyosup Won, Taeho Kim, Sejun Jeon, Soon-Won Kwon, Ha-Il Song, Hanho Choi, Bongjin Kim, Huxian Jin, Jun-Gi Jo, Woosang Han, Tai-Young Kim, Gain Kim, Jake Eu, Jinho Park, Hyeon-Min Bae
2024 J jnl
A Dual 7T SRAM-Based Zero-Skipping Compute- In-Memory Macro With 1-6b Binary Searching ADCs for Processing Quantized Neural Networks.
IEEE Trans. Circuits Syst. I Regul. Pap.
Chengshuo Yu, Haoge Jiang, Junjie Mu, Kevin Tshun Chuan Chai, Tony Tae-Hyoung Kim, Bongjin Kim
2024 J jnl
A Scalable and Reconfigurable Bit-Serial Compute-Near-Memory Hardware Accelerator for Solving 2-D/3-D Partial Differential Equations.
IEEE J. Solid State Circuits
Junjie Mu, Chengshuo Yu, Tony Tae-Hyoung Kim, Bongjin Kim
2024 J jnl
CTLE-Ising: A Continuous-Time Latch-Based Ising Machine Featuring One-Shot Fully Parallel Spin Updates and Equalization of Spin States.
IEEE J. Solid State Circuits
Jooyoung Bae, Wonsik Oh, Jahyun Koo, Chengshuo Yu, Bongjin Kim
2024 J jnl
FlexSpin: A CMOS Ising Machine With 256 Flexible Spin Processing Elements With 8-b Coefficients for Solving Combinatorial Optimization Problems.
IEEE J. Solid State Circuits
Yuqi Su, Tony Tae-Hyoung Kim, Bongjin Kim
2024 — conf
Quantized Context Based LIF Neurons for Recurrent Spiking Neural Networks in 45nm.
NICE
Sai Sukruth Bezugam, Yihao Wu, JaeBum Yoo, Dmitri B. Strukov, Bongjin Kim
2024 J jnl
Quantized Context Based LIF Neurons for Recurrent Spiking Neural Networks in 45nm.
CoRR
Sai Sukruth Bezugam, Yihao Wu, JaeBum Yoo, Dmitri B. Strukov, Bongjin Kim
2024 — conf
ROC-Spin: A 28nm 2, 000 Ring-Oscillator-Collapse Spins for Solving Combinatorial Optimization Problems.
A-SSCC
Yuqi Su, Anh Tuan Do, Tony Tae-Hyoung Kim, Bongjin Kim
2023 C conf
282-to-607 TOPS/W, 7T-SRAM Based CiM with Reconfigurable Column SAR ADC for Neural Network Processing.
ISCAS
Qibang Zang, Wang Ling Goh, Lu Lu, Chengshuo Yu, Junjie Mu, Tony Tae-Hyoung Kim, Bongjin Kim, Dongrui Li, Anh Tuan Do
2023 J jnl
A 1-16b Reconfigurable 80Kb 7T SRAM-Based Digital Near-Memory Computing Macro for Processing Neural Networks.
IEEE Trans. Circuits Syst. I Regul. Pap.
Hyunjoon Kim, Junjie Mu, Chengshuo Yu, Tony Tae-Hyoung Kim, Bongjin Kim
2023 — conf
A Bit-Serial Computing Accelerator for Solving Coupled Partial Differential Equations.
VLSI Technology and Circuits
Junjie Mu, Chengshuo Yu, Tony Tae-Hyoung Kim, Bongjin Kim
2023 — conf
A Continuous-Time Ising Machine using Coupled Inverter Chains Featuring Fully-Parallel One-Shot Spin Updates.
CICC
Chengshuo Yu, Junjie Mu, Kevin Tshun-Chuan Chai, Tony T. Kim, Bongjin Kim
2023 J jnl
A Dynamic-Precision Bit-Serial Computing Hardware Accelerator for Solving Partial Differential Equations Using Finite Difference Method.
IEEE J. Solid State Circuits
Junjie Mu, Bongjin Kim
2023 C conf
A Graph-Based Accelerator of Retinex Model with Bit-Serial Computing for Image Processing.
ISCAS
Zhengzhe Wei, Junjie Mu, Zhongzhiguang Lu, Yuanjin Zheng, Tony Tae-Hyoung Kim, Bongjin Kim
2023 — conf
A Reconfigurable lsing Machine for Boolean Satisfiability Problems Featuring Many-Body Spin Interactions.
CICC
Yuqi Su, Tony Tae-Hyoung Kim, Bongjin Kim
2023 J jnl
A Time-Domain Wavefront Computing Accelerator With a 32 × 32 Reconfigurable PE Array.
IEEE J. Solid State Circuits
Chengshuo Yu, Junjie Mu, Yuqi Su, Kevin Tshun Chuan Chai, Tony Tae-Hyoung Kim, Bongjin Kim
2023 — conf
CTLE-Ising:A 1440-Spin Continuous-Time Latch-Based isling Machine with One-Shot Fully-Parallel Spin Updates Featuring Equalization of Spin States.
ISSCC
Jooyoung Bae, Wonsik Oh, Jahyun Koo, Bongjin Kim
2023 J jnl
ReDCIM: Reconfigurable Digital Computing- In -Memory Processor With Unified FP/INT Pipeline for Cloud AI Acceleration.
IEEE J. Solid State Circuits
Fengbin Tu, Yiqi Wang, Zihan Wu, Ling Liang, Yufei Ding, Bongjin Kim, Leibo Liu, Shaojun Wei, Yuan Xie, Shouyi Yin
2022 — conf
A 28nm 29.2TFLOPS/W BF16 and 36.5TOPS/W INT8 Reconfigurable Digital CIM Processor with Unified FP/INT Pipeline and Bitwise In-Memory Booth Multiplication for Cloud Deep Learning Acceleration.
ISSCC
Fengbin Tu, Yiqi Wang, Zihan Wu, Ling Liang, Yufei Ding, Bongjin Kim, Leibo Liu, Shaojun Wei, Yuan Xie, Shouyi Yin
2022 J jnl
A 65-nm 8T SRAM Compute-in-Memory Macro With Column ADCs for Processing Neural Networks.
IEEE J. Solid State Circuits
Chengshuo Yu, Taegeun Yoo, Kevin Tshun Chuan Chai, Tony Tae-Hyoung Kim, Bongjin Kim
2022 — conf
A Scalable Bit-Serial Computing Hardware Accelerator for Solving 2D/3D Partial Differential Equations Using Finite Difference Method.
ESSCIRC
Junjie Mu, Chengshuo Yu, Tony Tae-Hyoung Kim, Bongjin Kim
2022 J jnl
A Scalable CMOS Ising Computer Featuring Sparse and Reconfigurable Spin Interconnects for Solving Combinatorial Optimization Problems.
IEEE J. Solid State Circuits
Yuqi Su, Junjie Mu, Hyunjoon Kim, Bongjin Kim
2022 J jnl
An Overview of Processing-in-Memory Circuits for Artificial Intelligence and Machine Learning.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Donghyuk Kim, Chengshuo Yu, Shanshan Xie, Yuzong Chen, Joo-Young Kim, Bongjin Kim, Jaydeep P. Kulkarni, Tony Tae-Hyoung Kim
2022 J jnl
CIM-Spin: A Scalable CMOS Annealing Processor With Digital In-Memory Spin Operators and Register Spins for Combinatorial Optimization Problems.
IEEE J. Solid State Circuits
Yuqi Su, Hyunjoon Kim, Bongjin Kim
2022 — conf
FlexSpin: A Scalable CMOS Ising Machine with 256 Flexible Spin Processing Elements for Solving Complex Combinatorial Optimization Problems.
ISSCC
Yuqi Su, Tony Tae-Hyoung Kim, Bongjin Kim
2022 J jnl
Guest Editorial Revolution of AI and Machine Learning With Processing-in-Memory (PIM): From Systems, Architectures, to Circuits.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Tony Tae-Hyoung Kim, Bongjin Kim, Joo-Young Kim, Jaydeep P. Kulkarni
2022 J jnl
SRAM-Based In-Memory Computing Macro Featuring Voltage-Mode Accumulator and Row-by-Row ADC for Processing Neural Networks.
IEEE Trans. Circuits Syst. I Regul. Pap.
Junjie Mu, Hyunjoon Kim, Bongjin Kim
2021 — conf
A 20x28 Spins Hybrid In-Memory Annealing Computer Featuring Voltage-Mode Analog Spin Operator for Solving Combinatorial Optimization Problems.
VLSI Circuits
Junjie Mu, Yuqi Su, Bongjin Kim
2021 — conf
A 21×21 Dynamic-Precision Bit-Serial Computing Graph Accelerator for Solving Partial Differential Equations Using Finite Difference Method.
ISSCC
Junjie Mu, Bongjin Kim
2021 — conf
A 252 Spins Scalable CMOS Ising Chip Featuring Sparse and Reconfigurable Spin Interconnects for Combinatorial Optimization Problems.
CICC
Yuqi Su, Junjie Mu, Hyunjoon Kim, Bongjin Kim
2021 — conf
A 32x32 Time-Domain Wavefront Computing Accelerator for Path Planning and Scientific Simulations.
CICC
Chengshuo Yu, Yuqi Su, Jaeho Lee, Kevin T. C. Chai, Bongjin Kim
2021 J jnl
A Logic-Compatible eDRAM Compute-In-Memory With Embedded ADCs for Processing Neural Networks.
IEEE Trans. Circuits Syst. I Regul. Pap.
Chengshuo Yu, Taegeun Yoo, Hyunjoon Kim, Tony Tae-Hyoung Kim, Kevin Chai Tshun Chuan, Bongjin Kim
2021 J jnl
A Reconfigurable 4T2R ReRAM Computing In-Memory Macro for Efficient Edge Applications.
IEEE Open J. Circuits Syst.
Yuzong Chen, Lu Lu, Bongjin Kim, Tony Tae-Hyoung Kim
2021 — conf
A Zero-Skipping Reconfigurable SRAM In-Memory Computing Macro with Binary-Searching ADC.
ESSCIRC
Chengshuo Yu, Kevin Tshun Chuan Chai, Tony Tae-Hyoung Kim, Bongjin Kim
2021 — conf
A Zero-Skipping Reconfigurable SRAM In-Memory Computing Macro with Binary-Searching ADC.
ESSDERC
Chengshuo Yu, Kevin Tshun Chuan Chai, Tony Tae-Hyoung Kim, Bongjin Kim
2021 J jnl
Colonnade: A Reconfigurable SRAM-Based Digital Bit-Serial Compute-In-Memory Macro for Processing Neural Networks.
IEEE J. Solid State Circuits
Hyunjoon Kim, Taegeun Yoo, Tony Tae-Hyoung Kim, Bongjin Kim
2020 — conf
31.2 CIM-Spin: A 0.5-to-1.2V Scalable Annealing Processor Using Digital Compute-In-Memory Spin Operators and Register-Based Spins for Combinatorial Optimization Problems.
ISSCC
Yuqi Su, Hyunjoon Kim, Bongjin Kim
2020 — conf
A 16K Current-Based 8T SRAM Compute-In-Memory Macro with Decoupled Read/Write and 1-5bit Column ADC.
CICC
Chengshuo Yu, Taegeun Yoo, Tony Tae-Hyoung Kim, Kevin Tshun Chuan Chai, Bongjin Kim
2020 A conf
A 16×128 Stochastic-Binary Processing Element Array for Accelerating Stochastic Dot-Product Computation Using 1-16 Bit-Stream Length.
DATE
Qian Chen, Yuqi Su, Hyunjoon Kim, Taegeun Yoo, Tony Tae-Hyoung Kim, Bongjin Kim
2020 C conf
A 3GS/s Highly Linear Energy Efficient Constant-Slope Based Voltage-to-Time Converter.
ISCAS
Qian Chen, Yuan Liang, Bongjin Kim, Chirn Chye Boon
2020 C conf
A 65nm Logic-Compatible Embedded and Flash Memory for In-Memory Computation of Artificial Neural Networks.
ISCAS
Junjie Mu, Bongjin Kim
2020 — conf
Design of Current-Mode 8T SRAM Compute-In-Memory Macro for Processing Neural Networks.
ISOCC
Taegeun Yoo, Tony Tae-Hyoung Kim, Bongjin Kim, Chengshuo Yu, Kevin Chai Tshun Chuan
2020 J jnl
Reconfigurable 2T2R ReRAM Architecture for Versatile Data Storage and Computing In-Memory.
IEEE Trans. Very Large Scale Integr. Syst.
Yuzong Chen, Lu Lu, Bongjin Kim, Tony Tae-Hyoung Kim
2020 C conf
Reconfigurable 2T2R ReRAM with Split Word-Lines for TCAM Operation and In-Memory Computing.
ISCAS
Yuzong Chen, Lu Lu, Bongjin Kim, Tony Tae-Hyoung Kim
2019 — conf
A 1-16b Precision Reconfigurable Digital In-Memory Computing Macro Featuring Column-MAC Architecture and Bit-Serial Computation.
ESSCIRC
Hyunjoon Kim, Qian Chen, Taegeun Yoo, Tony Tae-Hyoung Kim, Bongjin Kim
2019 — conf
A 16K SRAM-Based Mixed-Signal In-Memory Computing Macro Featuring Voltage-Mode Accumulator and Row-by-Row ADC.
A-SSCC
Hyunjoon Kim, Qian Chen, Bongjin Kim
2019 — conf
A Bit-Precision Reconfigurable Digital In-Memory Computing Macro for Energy-Efficient Processing of Artificial Neural Networks.
ISOCC
Hyunjoon Kim, Qian Chen, Taegeun Yoo, Tony Tae-Hyoung Kim, Bongjin Kim
2019 A conf
A Logic Compatible 4T Dual Embedded DRAM Array for In-Memory Computation of Deep Neural Networks.
ISLPED
Taegeun Yoo, Hyunjoon Kim, Qian Chen, Tony Tae-Hyoung Kim, Bongjin Kim
2019 — conf
Mixed-Signal Circuits and Architectures for Energy-Efficient In-Memory and In-Sensor Computation of Artificial Neural Networks.
SoCC
Bongjin Kim
2018 — conf
A 28Gb/s transceiver with chirp-managed EDC for DML systems.
ISSCC
Kyeongha Kwon, Jong-Hyeok Yoon, Hanho Choi, Younho Jeon, Jaehyeok Yang, Bongjin Kim, Soon-Won Kwon, Minsik Kim, Sejun Jeon, Hyosup Won, Hyeon-Min Bae
2018 — conf
All-digital PLL frequency and phase noise degradation measurements using simple on-chip monitoring circuits.
IRPS
Gyusung Park, Minsu Kim, Chris H. Kim, Bongjin Kim, Vijay Reddy
2017 J jnl
A 0.2-1.45-GHz Subsampling Fractional-N Digital MDLL With Zero-Offset Aperture PD-Based Spur Cancellation and In Situ Static Phase Offset Detection.
IEEE J. Solid State Circuits
Somnath Kundu, Bongjin Kim, Chris H. Kim
2016 — conf
19.2 A 0.2-to-1.45GHz subsampling fractional-N all-digital MDLL with zero-offset aperture PD-based spur cancellation and in-situ timing mismatch detection.
ISSCC
Somnath Kundu, Bongjin Kim, Chris H. Kim
2015 — conf
A 0.4-1.6GHz spur-free bang-bang digital PLL in 65nm with a D-flip-flop based frequency subtractor circuit.
VLSIC
Bongjin Kim, Somnath Kundu, Chris H. Kim
2015 — conf
An 8bit, 2.6ps two-step TDC in 65nm CMOS employing a switched ring-oscillator based time amplifier.
CICC
Bongjin Kim, Hoon Ki Kim, Chris H. Kim
2015 J jnl
Low-Complexity Tree Architecture for Finding the First Two Minima.
IEEE Trans. Circuits Syst. II Express Briefs
Youngjoo Lee, Bongjin Kim, Jaehwan Jung, In-Cheol Park
2015 J jnl
Reverse Rate Matching for Low-Power LTE-Advanced Turbo Decoders.
IEEE Trans. Circuits Syst. I Regul. Pap.
Injae Yoo, Bongjin Kim, In-Cheol Park
2015 — conf
Two-step beat frequency quantizer based ADC with adaptive reference control for low swing bio-potential signals.
CICC
Somnath Kundu, Bongjin Kim, Chris H. Kim
2014 J jnl
A Supply-Noise Sensitivity Tracking PLL in 32 nm SOI Featuring a Deep Trench Capacitor Based Loop Filter.
IEEE J. Solid State Circuits
Bongjin Kim, Weichao Xu, Chris H. Kim
2014 — conf
A VCO-based ADC employing a multi-phase noise-shaping beat frequency quantizer for direct sampling of Sub-1mV input signals.
CICC
Bongjin Kim, Somnath Kundu, Seokkyun Ko, Chris H. Kim
2014 J jnl
Low-Complexity Low-Latency Architecture for Matching of Data Encoded With Hard Systematic Error-Correcting Codes.
IEEE Trans. Very Large Scale Integr. Syst.
Byeong Yong Kong, Jihyuck Jo, Hyewon Jeong, Mina Hwang, Soyoung Cha, Bongjin Kim, In-Cheol Park
2014 J jnl
Tail-Overlapped SISO Decoding for High-Throughput LTE-Advanced Turbo Decoders.
IEEE Trans. Circuits Syst. I Regul. Pap.
Injae Yoo, Bongjin Kim, In-Cheol Park
2014 — conf
True Random Number Generator circuits based on single- and multi-phase beat frequency detection.
CICC
Qianying Tang, Bongjin Kim, Yingjie Lao, Keshab K. Parhi, Chris H. Kim
2013 — conf
A fully-digital beat-frequency based ADC achieving 39dB SNDR for a 1.6mVpp input signal.
CICC
Bongjin Kim, Weichao Xu, Chris H. Kim
2013 J jnl
Area-Efficient QC-LDPC Decoder Architecture Based on Stride Scheduling and Memory Bank Division.
IEICE Trans. Commun.
Bongjin Kim, In-Cheol Park
2013 J jnl
Low-Complexity Parallel QPP Interleaver Based on Permutation Patterns.
IEEE Trans. Circuits Syst. II Express Briefs
Bongjin Kim, Injae Yoo, In-Cheol Park
2013 — conf
Memory-Optimized Hybrid Decoding Method for Multi-Rate Turbo Codes.
VTC Spring
Injae Yoo, Bongjin Kim, In-Cheol Park
2012 J jnl
Design, Modeling, and Test of a Programmable Adaptive Phase-Shifting PLL for Enhancing Clock Data Compensation.
IEEE J. Solid State Circuits
Dong Jiao, Bongjin Kim, Chris H. Kim
2012 J jnl
Immediate Exchange of Extrinsic Information for High-Throughput Turbo Decoding.
IEEE Commun. Lett.
Injae Yoo, Bongjin Kim, In-Cheol Park
2012 A conf
Optimization of on-chip switched-capacitor DC-DC converters for high-performance applications.
ICCAD
Pingqiang Zhou, Won Ho Choi, Bongjin Kim, Chris H. Kim, Sachin S. Sapatnekar
2011 C conf
QC-LDPC Decoding Architecture based on Stride Scheduling.
ISCAS
Bongjin Kim, In-Cheol Park
2010 C conf
Dual-rail decoding of low-density parity-check codes.
ISCAS
Bongjin Kim, Hasan Ahmed, In-Cheol Park
2008 — conf
A 65nm 3.4Gbps HDMI TX PHY with supply-regulated dual-tuning PLL and blending multiplexer.
CICC
Jongshin Shin, Jaehyun Park, Bongjin Kim, Jongjae Ryu, Chiwon Kim, Jiyoung Kim, Seung-Hee Yang, Hyungoo Kim, Jaewhui Kim
2004 J jnl
Integral transforms, convolution products, and first variations.
Int. J. Math. Math. Sci.
Bongjin Kim, Byoung Soo Kim, David L. Skoug