| Year | Rank | Type | Title / Venue / Authors |
|---|---|---|---|
| 2026 | J | jnl |
Neurocomputing
|
| 2025 | J | jnl |
IEEE J. Solid State Circuits
|
| 2025 | J | jnl |
Knowl. Based Syst.
|
| 2025 | J | jnl |
Comput. Secur.
|
| 2025 | J | jnl |
IEEE J. Solid State Circuits
|
| 2025 | J | jnl |
CoRR
|
| 2025 | J | jnl |
Neurocomputing
|
| 2025 | J | jnl |
CoRR
|
| 2025 | J | jnl |
Comput. Commun.
|
| 2025 | J | jnl |
CoRR
|
| 2024 | J | jnl |
IEEE J. Solid State Circuits
|
| 2024 | B | conf |
IJCNN
|
| 2024 | — | conf |
ICA3PP (6)
|
| 2024 | A* | conf |
ICML
|
| 2023 | — | conf |
ESSCIRC
|
| 2023 | — | conf |
Compute SNR-boosted 22 nm MRAM-based In-memory Computing Macro using Statistical Error Compensation.
ESSCIRC
|
| 2022 | — | conf |
VLSI Technology and Circuits
|
| 2022 | A* | conf |
DAC
|
| 2021 | — | conf |
ESSCIRC
|
| 2021 | — | conf |
ESSDERC
|
| 2021 | — | conf |
CSS
|
| 2021 | J | jnl |
IEEE Trans. Circuits Syst. I Regul. Pap.
|
| 2019 | Misc | conf |
ICASSP
|