Bob Verbruggen

35 papers Journal 15Unranked 20

Year	Rank	Type	Title / Venue / Authors
2021	—	`conf`	Session 27 Overview: Discrete-Time ADCs Data Converters Subcommittee. ISSCC John Keane, Chih-Cheng Hsieh, Bob Verbruggen
2019	J	`jnl`	Introduction to the Special Issue on the 2019 IEEE International Solid-State Circuits Conference (ISSCC). IEEE J. Solid State Circuits Youngcheol Chae, Bernhard Wicht, Bob Verbruggen, Payam Heydari, Howard C. Luong
2018	—	`conf`	A 13Bit 5GS/S ADC with Time-Interleaved Chopping Calibration in 16NM FinFET. VLSI Circuits Bruno Vaz, Bob Verbruggen, Christophe Erdmann, Diarmuid Collins, John McGrath, Ali Boumaalif, Edward Cullen, Darragh Walsh, Alonso Morgado, Conrado Mesadri, Brian Long, Rajitha Pathepuram, Ronnie De La Torre, Alvin Manlapat, Georgios Karyotis, Dimitris Tsaliagos, Patrick Lynch, Peng Lim, Daire Breathnach, Brendan Farley
2018	—	`conf`	A 7.4-to-14GHz PLL with 54fsrms jitter in 16nm FinFET for integrated RF-data-converter SoCs. ISSCC Didem Turker, Ade Bekele, Parag Upadhyaya, Bob Verbruggen, Ying Cao, Shaojun Ma, Christophe Erdmann, Brendan Farley, Yohan Frans, Ken Chang
2018	—	`conf`	A modular 16NM Direct-RF TX/RX Embedding 9GS/S DAC and 4.5GS/S ADC with 90DB Isolation and Sub-80PS Channel Alignment for Monolithic Integration in 5G Base-Station SoC. VLSI Circuits Christophe Erdmann, Bob Verbruggen, Bruno Vaz, Roberto Pelliconi, John McGrath, Ryan Kinnerk, Ronnie De La Torre, John O'Dwyer, Patrick Lynch, Padraig Kelly, Peng Lim, Daire Breathnach, Brendan Farley
2017	—	`conf`	16.1 A 13b 4GS/s digitally assisted dynamic 3-stage asynchronous pipelined-SAR ADC. ISSCC Bruno Vaz, Adrian Lynam, Bob Verbruggen, Asma Laraba, Conrado Mesadri, Ali Boumaalif, John McGrath, Umanath Kamath, Ronnie De La Torre, Alvin Manlapat, Daire Breathnach, Christophe Erdmann, Brendan Farley
2017	—	`conf`	16.3 A 330mW 14b 6.8GS/s dual-mode RF DAC in 16nm FinFET achieving -70.8dBc ACPR in a 20MHz channel at 5.2GHz. ISSCC Christophe Erdmann, Edward Cullen, Damien Brouard, Roberto Pelliconi, Bob Verbruggen, John McGrath, Diarmuid Collins, Marites De La Torre, Pierrick Gay, Patrick Lynch, Peng Lim, Anthony Collins, Brendan Farley
2017	—	`conf`	A programmable RFSoC in 16nm FinFET technology for wideband communications. A-SSCC Brendan Farley, Christophe Erdmann, Bruno Vaz, John McGrath, Edward Cullen, Bob Verbruggen, Roberto Pelliconi, Daire Breathnach, Peng Lim, Ali Boumaalif, Patrick Lynch, Conrado Mesadri, David Melinn, Kwee Peng Yap, Liam Madden
2017	—	`conf`	Session 28 overview: Hybrid ADCs. ISSCC Tai-Cheng Lee, Bob Verbruggen, Un-Ku Moon
2016	J	`jnl`	A 150 kHz-80 MHz BW Discrete-Time Analog Baseband for Software-Defined-Radio Receivers using a 5th-Order IIR LPF, Active FIR and a 10 bit 300 MS/s ADC in 28 nm CMOS. IEEE J. Solid State Circuits Badr Malki, Bob Verbruggen, Ewout Martens, Piet Wambacq, Jan Craninckx
2016	J	`jnl`	Digitally Modulated CMOS Polar Transmitters for Highly-Efficient mm-Wave Wireless Communication. IEEE J. Solid State Circuits Khaled Khalaf, Vojkan Vidojkovic, Kristof Vaesen, Michael Libois, Giovanni Mangraviti, Viki Szortyka, Chunshu Li, Bob Verbruggen, Mark Ingels, André Bourdoux, Charlotte Soens, Wim Van Thillo, John R. Long, Piet Wambacq
2015	—	`conf`	A 150 kHz-80 MHz BW DT analog baseband for SDR RX using a 5 ESSCIRC Badr Malki, Bob Verbruggen, Ewout Martens, Piet Wambacq, Jan Craninckx
2015	J	`jnl`	A 60 dB SNDR 35 MS/s SAR ADC With Comparator-Noise-Based Stochastic Residue Estimation. IEEE J. Solid State Circuits Bob Verbruggen, Jorgo Tsouhlarakis, Takaya Yamamoto, Masao Iriguchi, Ewout Martens, Jan Craninckx
2015	J	`jnl`	Correction to "A 70 dB DR 10 b 0-to-80 MS/s Current-Integrating SAR ADC With Adaptive Dynamic Range". IEEE J. Solid State Circuits Badr Malki, Takaya Yamamoto, Bob Verbruggen, Piet Wambacq, Jan Craninckx
2015	—	`conf`	High-speed analog-to-digital converters in downscaled CMOS. ICICDT Annachiara Spagnolo, Bob Verbruggen, Stefano D'Amico, Piet Wambacq
2014	J	`jnl`	A 0.9 V 0.4-6 GHz Harmonic Recombination SDR Receiver in 28 nm CMOS With HR3/HR5 and IIP2 Calibration. IEEE J. Solid State Circuits Barend van Liempd, Jonathan Borremans, Ewout Martens, Sungwoo Cha, Hans Suys, Bob Verbruggen, Jan Craninckx
2014	J	`jnl`	A 4.1-mW 3.5-GS/s 6-Bit Time-Interleaved ADC in 40-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs Annachiara Spagnolo, Bob Verbruggen, Piet Wambacq, Stefano D'Amico
2014	—	`conf`	A 6.2mW 7b 3.5GS/s time interleaved 2-stage pipelined ADC in 40nm CMOS. ESSCIRC Annachiara Spagnolo, Bob Verbruggen, Stefano D'Amico, Piet Wambacq
2014	J	`jnl`	A 70 dB DR 10 b 0-to-80 MS/s Current-Integrating SAR ADC With Adaptive Dynamic Range. IEEE J. Solid State Circuits Badr Malki, Takaya Yamamoto, Bob Verbruggen, Piet Wambacq, Jan Craninckx
2014	—	`conf`	A 70 dB SNDR 200 MS/s 2.3 mW dynamic pipelined SAR ADC in 28nm digital CMOS. VLSIC Bob Verbruggen, Kazuaki Deguchi, Badr Malki, Jan Craninckx
2014	—	`conf`	A complementary dynamic residue amplifier for a 67 dB SNDR 1.36 mW 170 MS/s pipelined SAR ADC. ESSCIRC Badr Malki, Bob Verbruggen, Piet Wambacq, Kazuaki Deguchi, Masao Iriguchi, Jan Craninckx
2012	J	`jnl`	A 1.7 mW 11b 250 MS/s 2-Times Interleaved Fully Dynamic Pipelined SAR ADC in 40 nm Digital CMOS. IEEE J. Solid State Circuits Bob Verbruggen, Masao Iriguchi, Jan Craninckx
2012	—	`conf`	A 1.7mW 11b 250MS/s 2× interleaved fully dynamic pipelined SAR ADC in 40nm digital CMOS. ISSCC Bob Verbruggen, Masao Iriguchi, Jan Craninckx
2012	—	`conf`	A 70dB DR 10b 0-to-80MS/s current-integrating SAR ADC with adaptive dynamic range. ISSCC Badr Malki, Takaya Yamamoto, Bob Verbruggen, Piet Wambacq, Jan Craninckx
2011	J	`jnl`	A 40 nm CMOS 0.4-6 GHz Receiver Resilient to Out-of-Band Blockers. IEEE J. Solid State Circuits Jonathan Borremans, Gunjan Mandal, Vito Giannini, Björn Debaillie, Mark Ingels, Tomohiro Sano, Bob Verbruggen, Jan Craninckx
2011	—	`conf`	A 40nm CMOS highly linear 0.4-to-6GHz receiver resilient to 0dBm out-of-band blockers. ISSCC Jonathan Borremans, Gunjan Mandal, Vito Giannini, Tomohiro Sano, Mark Ingels, Bob Verbruggen, Jan Craninckx
2010	J	`jnl`	A 2.6 mW 6 bit 2.2 GS/s Fully Dynamic Pipeline ADC in 40 nm Digital CMOS. IEEE J. Solid State Circuits Bob Verbruggen, Jan Craninckx, Maarten Kuijk, Piet Wambacq, Geert Van der Plas
2010	—	`conf`	A 2.6mW 6b 2.2GS/s 4-times interleaved fully dynamic pipelined ADC in 40nm digital CMOS. ISSCC Bob Verbruggen, Jan Craninckx, Maarten Kuijk, Piet Wambacq, Geert Van der Plas
2009	J	`jnl`	A 2.2 mW 1.75 GS/s 5 Bit Folding Flash ADC in 90 nm Digital CMOS. IEEE J. Solid State Circuits Bob Verbruggen, Jan Craninckx, Maarten Kuijk, Piet Wambacq, Geert Van der Plas
2009	J	`jnl`	A 2.4 GHz Low-Power Sixth-Order RF Bandpass ΔΣ Converter in CMOS. IEEE J. Solid State Circuits Julien Ryckaert, Jonathan Borremans, Bob Verbruggen, Lynn Bos, Costantino Armiento, Jan Craninckx, Geert Van der Plas
2008	J	`jnl`	A 150 MS/s 133 µW 7 bit ADC in 90 nm Digital CMOS. IEEE J. Solid State Circuits Geert Van der Plas, Bob Verbruggen
2008	—	`conf`	A 150MS/s 133μW 7b ADC in 90nm digital CMOS Using a Comparator-Based Asynchronous Binary-Search sub-ADC. ISSCC Geert Van der Plas, Bob Verbruggen
2008	—	`conf`	A 2.2mW 5b 1.75GS/s Folding Flash ADC in 90nm Digital CMOS. ISSCC Bob Verbruggen, Jan Craninckx, Maarten Kuijk, Piet Wambacq, Geert Van der Plas
2008	—	`conf`	Advanced Planar Bulk and Multigate CMOS Technology: Analog-Circuit Benchmarking up to mm-Wave Frequencies. ISSCC Piet Wambacq, Abdelkarim Mercha, Karen Scheir, Bob Verbruggen, Jonathan Borremans, Vincent De Heyn, Steven Thijs, Dimitri Linten, Geert Van der Plas, Bertrand Parvais, Morin Dehan, Stefaan Decoutere, Charlotte Soens, Nadine Collaert, Malgorzata Jurczak
2007	J	`jnl`	The Potential of FinFETs for Analog and RF Circuit Applications. IEEE Trans. Circuits Syst. I Regul. Pap. Piet Wambacq, Bob Verbruggen, Karen Scheir, Jonathan Borremans, Morin Dehan, Dimitri Linten, Vincent De Heyn, Geert Van der Plas, Abdelkarim Mercha, Bertrand Parvais, Cedric Gustin, Vaidyanathan Subramanian, Nadine Collaert, Malgorzata Jurczak, Stefaan Decoutere