Bo Yao - RankMe

19 papers A* 2A 2C 2Journal 4Unranked 8

Year	Rank	Type	Title / Venue / Authors
2011	J	`jnl`	On-Chip Interconnect Analysis of Performance and Energy Metrics Under Different Design Goals. IEEE Trans. Very Large Scale Integr. Syst. Ling Zhang, Yulei Zhang, Hongyu Chen, Bo Yao, Kevin Hamilton, Chung-Kuan Cheng
2007	J	`jnl`	Efficient Timing Analysis With Known False Paths Using Biclique Covering. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Shuo Zhou, Bo Yao, Hongyu Chen, Yi Zhu, Michael D. Hutton, Truman Collins, Sridhar Srinivasan, Nan-Chi Chou, Peter Suaris, Chung-Kuan Cheng
2007	—	`conf`	Repeated On-Chip Interconnect Analysis and Evaluation of Delay, Power, and Bandwidth Metrics under Different Design Goals. ISQED Ling Zhang, Hongyu Chen, Bo Yao, Kevin Hamilton, Chung-Kuan Cheng
2006	—	`conf`	Efficient static timing analysis using a unified framework for false paths and multi-cycle paths. ASP-DAC Shuo Zhou, Bo Yao, Hongyu Chen, Yi Zhu, Chung-Kuan Cheng, Michael D. Hutton
2005	A	`conf`	Improving the efficiency of static timing analysis with false paths. ICCAD Shuo Zhou, Bo Yao, Hongyu Chen, Yi Zhu, Chung-Kuan Cheng, Michael D. Hutton, Truman Collins, Sridhar Srinivasan, Nan-Chi Chou, Peter Suaris
2005	—	`conf`	Integrated algorithmic logical and physical design of integer multiplier. ASP-DAC Shuo Zhou, Bo Yao, Jianhua Liu, Chung-Kuan Cheng
2005	J	`jnl`	The Y architecture for on-chip interconnect: analysis and methodology. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Hongyu Chen, Chung-Kuan Cheng, Andrew B. Kahng, Ion I. Mandoiu, Qinke Wang, Bo Yao
2005	—	`conf`	Unified quadratic programming approach for mixed mode placement. ISPD Bo Yao, Hongyu Chen, Chung-Kuan Cheng, Nan-Chi Chou, Lung-Tien Liu, Peter Suaris
2004	—	`conf`	A multiple level network approach for clock skew minimization with process variations. ASP-DAC Makoto Mori, Hongyu Chen, Bo Yao, Chung-Kuan Cheng
2004	—	`ch.`	Floorplan Representation in VLSI. Handbook of Data Structures and Applications Zhou Feng, Bo Yao, Chung-Kuan Cheng
2003	—	`conf`	A hierarchical three-way interconnect architecture for hexagonal processors. SLIP Feng Zhou, Esther Y. Cheng, Bo Yao, Chung-Kuan Cheng, Ronald L. Graham
2003	A*	`conf`	An algebraic multigrid solver for analytical placement with layout based clustering. DAC Hongyu Chen, Chung-Kuan Cheng, Nan-Chi Chou, Andrew B. Kahng, John F. MacDonald, Peter Suaris, Bo Yao, Zhengyong Zhu
2003	J	`jnl`	Floorplan representations: Complexity and connections. ACM Trans. Design Autom. Electr. Syst. Bo Yao, Hongyu Chen, Chung-Kuan Cheng, Ronald L. Graham
2003	A*	`conf`	Power network analysis using an adaptive algebraic multigrid approach. DAC Zhengyong Zhu, Bo Yao, Chung-Kuan Cheng
2003	A	`conf`	The Y-Architecture for On-Chip Interconnect: Analysis and Methodology. ICCAD Hongyu Chen, Chung-Kuan Cheng, Andrew B. Kahng, Ion I. Mandoiu, Qinke Wang, Bo Yao
2003	—	`conf`	The Y-architecture: yet another on-chip interconnect solution. ASP-DAC Hongyu Chen, Bo Yao, Feng Zhou, Chung-Kuan Cheng
2002	C	`conf`	Balancing the Interconnect Topology for Arrays of Processors between Cost and Power. ICCD Esther Y. Cheng, Feng Zhou, Bo Yao, Chung-Kuan Cheng, Ronald L. Graham
2002	C	`conf`	Physical Planning Of On-Chip Interconnect Architectures. ICCD Hongyu Chen, Bo Yao, Feng Zhou, Chung-Kuan Cheng
2001	—	`conf`	Revisiting floorplan representations. ISPD Bo Yao, Hongyu Chen, Chung-Kuan Cheng, Ronald L. Graham