Bo Yang

23 papers A 1C 2Journal 8Unranked 12
YearRankTypeTitle / Venue / Authors
2018 J jnl
Routable and Matched Layout Styles for Analog Module Generation.
ACM Trans. Design Autom. Electr. Syst.
Bo Liu, Gong Chen, Bo Yang, Shigetoshi Nakatake
2016 J jnl
DC Characteristics and Variability on 90nm CMOS Transistor Array-Style Analog Layout.
ACM Trans. Design Autom. Electr. Syst.
Gong Chen, Toru Fujimura, Qing Dong, Shigetoshi Nakatake, Bo Yang
2016 — conf
Routability of twisted common-centroid capacitor array under signal coupling constraints.
MWSCAS
Gong Chen, Bo Liu, Shigetoshi Nakatake, Bo Yang
2016 — conf
Twin-row-style for MOS analog layout.
ICECS
Bo Liu, Shigetoshi Nakatake, Bo Yang, Gong Chen
2013 — conf
A 9-bit 50msps SAR ADC with pre-charge VCM -based double input range algorithm.
ACM Great Lakes Symposium on VLSI
Gong Chen, Bo Yang, Yu Zhang, Qing Dong, Shigetoshi Nakatake
2013 — conf
A comparator energy model considering shallow trench isolation stress by geometric programming.
ISQED
Gong Chen, Yu Zhang, Bo Yang, Qing Dong, Shigetoshi Nakatake
2013 J jnl
Analog Circuit Synthesis with Constraint Generation of Layout-Dependent Effects by Geometric Programming.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Yu Zhang, Gong Chen, Bo Yang, Jing Li, Qing Dong, Mingyu Li, Shigetoshi Nakatake
2013 J jnl
Structured Analog Circuit and Layout Design with Transistor Array.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Bo Yang, Qing Dong, Jing Li, Shigetoshi Nakatake
2012 C conf
A retargeting methodology of nano-watt CMOS reference circuit based on advanced compact MOSFET model.
ISCAS
Gong Chen, Bo Yang, Shigetoshi Nakatake, Zhangcai Huang, Yasuaki Inoue
2012 — conf
CMOS op-amp circuit synthesis with geometric programming models for layout-dependent effects.
ISQED
Yu Zhang, Bo Liu, Bo Yang, Jing Li, Shigetoshi Nakatake
2012 J jnl
Layout-Aware Variability Characterization of CMOS Current Sources.
IEICE Trans. Electron.
Bo Liu, Bo Yang, Shigetoshi Nakatake
2012 — conf
Transistor channel decomposition for structured analog layout, manufacturability and low-power applications.
ISQED
Qing Dong, Bo Yang, Gong Chen, Jing Li, Shigetoshi Nakatake
2011 — conf
Layout-aware mismatch modeling for CMOS current sources with D/A converter analysis.
ISQED
Bo Liu, Qing Dong, Bo Yang, Jing Li, Shigetoshi Nakatake
2011 — conf
Layout-aware variation evaluation of analog circuits and its validity on op-amp designs.
ACM Great Lakes Symposium on VLSI
Kota Shinohara, Mihoko Hidaka, Jing Li, Qing Dong, Bo Yang, Shigetoshi Nakatake
2010 — conf
D-A converter based variation analysis for analog layout design.
ASP-DAC
Bo Liu, Toru Fujimura, Bo Yang, Shigetoshi Nakatake
2010 C conf
Post-placement STI well width adjusting by geometric programming for device mobility enhancement in critical path.
ISCAS
Jing Li, Bo Yang, Qing Dong, Shigetoshi Nakatake
2010 A conf
Structured analog circuit design and MOS transistor decomposition for high accuracy applications.
ICCAD
Bo Yang, Qing Dong, Jing Li, Shigetoshi Nakatake
2009 J jnl
Fast Shape Optimization of Metalization Patterns for Power-MOSFET Based Driver.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Bo Yang, Shigetoshi Nakatake
2009 J jnl
Incremental Buffer Insertion and Module Resizing Algorithm Using Geometric Programming.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Qing Dong, Bo Yang, Jing Li, Shigetoshi Nakatake
2009 — conf
Incremental buffer insertion and module resizing algorithm using geometric programming.
ACM Great Lakes Symposium on VLSI
Qing Dong, Bo Yang, Jing Li, Shigetoshi Nakatake
2009 — conf
STI stress aware placement optimization based on geometric programming.
ACM Great Lakes Symposium on VLSI
Jing Li, Bo Yang, Xiaochuan Hu, Qing Dong, Shigetoshi Nakatake
2008 J jnl
A Finite Element-Domain Decomposition Coupled Resistance Extraction Method with Virtual Terminal Insertion.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Bo Yang, Hiroshi Murata, Shigetoshi Nakatake
2008 — conf
Fast Shape Optimization of Metallization Patterns for DMOS Based Driver.
ISQED
Bo Yang, Shigetoshi Nakatake, Hiroshi Murata