Bo Wang

28 papers A 1C 3Journal 13Unranked 11
YearRankTypeTitle / Venue / Authors
2026 J jnl
EMO-CIM: An Input/Stationary-Data Similarity-Aware Computing-In-Memory Design for Variable Vector-Wise Computation in Edge Multioperator AI Acceleration.
IEEE Solid State Circuits Lett.
Bo Wang, Yuchen Tang, Feiran Liu, Xiaoxue Zhong, Yuchen Ma, Xin Si, Jun Yang
2025 — conf
14.6 A 28nm 64kb Bit-Rotated Hybrid-CIM Macro with an Embedded Sign-Bit-Processing Array and a Multi-Bit-Fusion Dual-Granularity Cooperative Quantizer.
ISSCC
Xi Chen, Shaochen Li, Zhican Zhang, Wentao Zheng, Xiao Tan, Yuchen Tang, Yuhui Shi, Lizheng Ren, Yibo Mai, Feiran Liu, Jinwu Chen, Zhaoyang Zhang, An Guo, Tianzhu Xiong, Bo Wang, Xinning Liu, Weiwei Shan, Bo Liu, Hao Cai, Jun Yang, Xin Si
2025 — conf
14.7 NeuroPilot: A 28nm, 69.4fJ/node and 0.22ns/node, 32×32 Mimetic-Path-Searching CIM-Macro with Dynamic-Logic Pilot PE and Dual-Direction Searching.
ISSCC
An Guo, Jingmin Zhang, Xingyu Pu, Yi Yang, Defa Wu, Yuchen Tang, Yuhui Shi, Yinghai Gao, Zhichao Liu, Bo Wang, Tianzhu Xiong, Zhaoyang Zhang, Xi Chen, Jinwu Chen, Feiran Liu, Xing Wang, Xinning Liu, Weiwei Shan, Bo Liu, Hao Cai, Xin Si, Jun Yang
2025 J jnl
A 28-nm 16-kb Aggregation and Combination Computing-in-Memory Macro With Dual-Level Sparsity Modulation and Sparse-Tracking ADCs for GCNs.
IEEE J. Solid State Circuits
Zhaoyang Zhang, Yanqi Zhang, Feiran Liu, Zhichao Liu, Yinhai Gao, Yuchen Ma, Yutong Zhang, An Guo, Tianzhu Xiong, Jinwu Chen, Xi Chen, Bo Wang, Yuchen Tang, Jun Yang, Xin Si
2025 J jnl
Bridging the Gap: Self-Optimized Fine-Tuning for LLM-based Recommender Systems.
CoRR
Heng Tang, Feng Liu, Xinbo Chen, Jiawei Chen, Bo Wang, Changwang Zhang, Jun Wang, Yuegang Sun, Bingde Hu, Can Wang
2025 J jnl
VCD-CIM: A Vertical-Compute-Decode Digital Computing-In-Memory Area-Efficient Macro for Vector-Wise Computation With Variable Accumulation Length.
IEEE Access
Bo Wang, Xiaoxue Zhong, Jun Yang
2024 — conf
34.3 A 22nm 64kb Lightning-Like Hybrid Computing-in-Memory Macro with a Compressed Adder Tree and Analog-Storage Quantizers for Transformer and CNNs.
ISSCC
An Guo, Xi Chen, Fangyuan Dong, Jinwu Chen, Zhihang Yuan, Xing Hu, Yuanpeng Zhang, Jingmin Zhang, Yuchen Tang, Zhican Zhang, Gang Chen, Dawei Yang, Zhaoyang Zhang, Lizheng Ren, Tianzhu Xiong, Bo Wang, Bo Liu, Weiwei Shan, Xinning Liu, Hao Cai, Guangyu Sun, Jun Yang, Xin Si
2024 J jnl
A 22-nm 264-GOPS/mm
IEEE Trans. Very Large Scale Integr. Syst.
Feiran Liu, Anran Yin, Chen Xue, Bo Wang, Zhongyuan Feng, Han Liu, Xiang Li, Hui Gao, Tianzhu Xiong, Xin Si
2024 J jnl
A 28-nm 64-kb 31.6-TFLOPS/W Digital-Domain Floating-Point-Computing-Unit and Double-Bit 6T-SRAM Computing-in-Memory Macro for Floating-Point CNNs.
IEEE J. Solid State Circuits
An Guo, Chen Xi, Fangyuan Dong, Xingyu Pu, Dongqi Li, Jingmin Zhang, Xueshan Dong, Hui Gao, Yiran Zhang, Bo Wang, Jun Yang, Xin Si
2024 — conf
A 28nm 16kb Aggregation and Combination Computing-in-Memory Macro with Dual-level Sparsity Modulation and Sparse-Tracking ADCs for GCNs.
CICC
Zhaoyang Zhang, Zhichao Liu, Feiran Liu, Yinhai Gao, Yuchen Ma, Yutong Zhang, An Guo, Tianzhu Xiong, Jinwu Chen, Xi Chen, Bo Wang, Yuchen Tang, Xingyu Pu, Xing Wang, Jun Yang, Xin Si
2024 J jnl
Toggle Rate Aware Quantization Model Based on Digital Floating-Point Computing-In-Memory Architecture.
IEEE Trans. Circuits Syst. II Express Briefs
Xi Chen, Yitong Zhao, An Guo, Jinwu Chen, Fangyuan Dong, Zhaoyang Zhang, Tianzhu Xiong, Bo Wang, Yuyao Kong, Xin Si
2023 — conf
A 28nm 64-kb 31.6-TFLOPS/W Digital-Domain Floating-Point-Computing-Unit and Double-Bit 6T-SRAM Computing-in-Memory Macro for Floating-Point CNNs.
ISSCC
An Guo, Xin Si, Xi Chen, Fangyuan Dong, Xingyu Pu, Dongqi Li, Yongliang Zhou, Lizheng Ren, Yeyang Xue, Xueshan Dong, Hui Gao, Yiran Zhang, Jingmin Zhang, Yuyao Kong, Tianzhu Xiong, Bo Wang, Hao Cai, Weiwei Shan, Jun Yang
2023 — conf
A 28nm Horizontal-Weight-Shift and Vertical-feature-Shift-Based Separate-WL 6T-SRAM Computation-in-Memory Unit-Macro for Edge Depthwise Neural-Networks.
ISSCC
Bo Wang, Chen Xue, Zhongyuan Feng, Zhaoyang Zhang, Han Liu, Lizheng Ren, Xiang Li, Anran Yin, Tianzhu Xiong, Yeyang Xue, Shengnan He, Yuyao Kong, Yongliang Zhou, An Guo, Xin Si, Jun Yang
2023 — conf
Evaluation Model for Current-Domain SRAM-based Computing-in-Memory Circuits.
MCSoC
Yiran Zhang, Bo Wang, Jinwu Chen, Xi Chen, Xin Si
2023 J jnl
From macro to microarchitecture: reviews and trends of SRAM-based compute-in-memory circuits.
Sci. China Inf. Sci.
Zhaoyang Zhang, Jinwu Chen, Xi Chen, An Guo, Bo Wang, Tianzhu Xiong, Yuyao Kong, Xingyu Pu, Shengnan He, Xin Si, Jun Yang
2022 — conf
A Booth-based Digital Compute-in-Memory Marco for Processing Transformer Model.
APCCAS
Zhongyuan Feng, Bo Wang, Zhaoyang Zhang, An Guo, Xin Si
2022 C conf
SNNIM: A 10T-SRAM based Spiking-Neural-Network-In-Memory architecture with capacitance computation.
ISCAS
Bo Wang, Chen Xue, Han Liu, Xiang Li, Anran Yin, Zhongyuan Feng, Yuyao Kong, Tianzhu Xiong, Haiming Hsu, Yongliang Zhou, An Guo, Yufei Wang, Jun Yang, Xin Si
2022 C conf
ShareFloat CIM: A Compute-In-Memory Architecture with Floating-Point Multiply-and-Accumulate Operations.
ISCAS
An Guo, Yongliang Zhou, Bo Wang, Tianzhu Xiong, Chen Xue, Yufei Wang, Xin Si, Jun Yang
2021 — conf
Design Challenges and Methodology of High-Performance SRAM-Based Compute-in-Memory for AI Edge Devices.
UCET
Yufei Wang, Yongliang Zhou, Bo Wang, Tianzhu Xiong, Yuyao Kong, Xin Si
2021 — conf
Design Methodology towards High-Precision SRAM based Computation-in-Memory for AI Edge Devices.
ISOCC
Tianzhu Xiong, Yongliang Zhou, Yuyao Kong, Bo Wang, An Guo, Yufei Wang, Chen Xue, Haiming Hsu, Xin Si, Jun Yang
2020 J jnl
A 60 Gb/s-Level Coarse-Grained Reconfigurable Cryptographic Processor With Less Than 1-W Power.
IEEE Trans. Circuits Syst. II Express Briefs
Chenchen Deng, Bo Wang, Leibo Liu, Min Zhu, Youyu Wu, Hui Li, Shouyi Yin, Shaojun Wei
2019 — conf
Sandwich-RAM: An Energy-Efficient In-Memory BWN Architecture with Pulse-Width Modulation.
ISSCC
Jun Yang, Yuyao Kong, Zhen Wang, Yan Liu, Bo Wang, Shouyi Yin, Longxin Shi
2018 J jnl
Anole: A Highly Efficient Dynamically Reconfigurable Crypto-Processor for Symmetric-Key Algorithms.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Leibo Liu, Bo Wang, Chenchen Deng, Min Zhu, Shouyi Yin, Shaojun Wei
2017 J jnl
Exploration of Benes Network in Cryptographic Processors: A Random Infection Countermeasure for Block Ciphers Against Fault Attacks.
IEEE Trans. Inf. Forensics Secur.
Bo Wang, Leibo Liu, Chenchen Deng, Min Zhu, Shouyi Yin, Zhuoquan Zhou, Shaojun Wei
2016 J jnl
Against Double Fault Attacks: Injection Effort Model, Space and Time Randomization Based Countermeasures for Reconfigurable Array Architecture.
IEEE Trans. Inf. Forensics Secur.
Bo Wang, Leibo Liu, Chenchen Deng, Min Zhu, Shouyi Yin, Shaojun Wei
2016 J jnl
Dynamically reconfigurable architecture for symmetric ciphers.
Sci. China Inf. Sci.
Bo Wang, Leibo Liu
2015 C conf
A flexible and energy-efficient reconfigurable architecture for symmetric cipher processing.
ISCAS
Bo Wang, Leibo Liu
2015 A conf
REPROC: A Dynamically Reconfigurable Architecture for Symmetric Cryptography (Abstract Only).
FPGA
Bo Wang, Leibo Liu