Bo Liu

31 papers Journal 22Unranked 9
YearRankTypeTitle / Venue / Authors
2025 J jnl
EDRP-GTDQN: An adaptive routing protocol for energy and delay optimization in wireless sensor networks using game theory and deep reinforcement learning.
Ad Hoc Networks
Ning Liu, Jun Wang, Fazhan Tao, Zhumu Fu, Bo Liu
2025 J jnl
Nested chopper instrument amplifier with noise modulation for physiological signal sensing.
Integr.
Bo Liu, Dong Zhang, Tianyu Liu, Kai Li, Jinchan Wang, Jun Wang
2024 J jnl
A 1.8 V 115.52 dB Third-Order Discrete-Time Sigma-Delta Modulator Using Nested Chopper Technology.
J. Circuits Syst. Comput.
Jinchan Wang, Gefan Wang, Kai Li, Bo Liu
2024 J jnl
Erratum: A 1.8 V 115.52 dB Third-Order Discrete-Time Sigma-Delta Modulator Using Nested Chopper Technology.
J. Circuits Syst. Comput.
Jinchan Wang, Gefan Wang, Kai Li, Bo Liu
2024 J jnl
FDIA localization and classification detection in smart grids using multi-modal data and deep learning technique.
Comput. Electr. Eng.
Jun Wang, Haoran Chen, Yifei Si, Yongai Zhu, Tianci Zhu, Shanshan Yin, Bo Liu
2024 J jnl
Power-efficient wideband programmable pseudo differential ring oscillator CP-PLL.
Microelectron. J.
Bo Liu, He Yang, Xiangjun Wang, Ruizhi Xiang, Jun Wang, Liwen Zhang
2024 J jnl
Response surface methodology based synchronous multi-performance optimization of CMOS low-dropout regulator.
Microelectron. J.
Bo Liu, Pengfei Wang, Xiang Liu, Liwen Zhang
2023 J jnl
A multi-objective parameter optimization approach to maximize lifetime of wireless sensor networks inspired by spider web.
J. Supercomput.
Jun Wang, Yadan Zhang, Xichao Wang, Pengjun Mao, Bo Liu
2023 J jnl
Adaptive particle swarm optimization based hybrid small-signal modeling of GaN HEMT.
Microelectron. J.
Haiyi Cai, Jincan Zhang, Min Liu, Shi Yang, Shaowei Wang, Bo Liu, Juwei Zhang
2023 J jnl
BP Neural Network Modeling and Solving Acceleration of Analog ICs.
Circuits Syst. Signal Process.
Bo Liu, Weizhe Zhang, Wenjuan Duan, Qingduan Meng
2023 J jnl
Discrimination strategy using machine learning technique for oestrus detection in dairy cows by a dual-channel-based acoustic tag.
Comput. Electron. Agric.
Jun Wang, Yifei Si, Jianping Wang, Xiaoxia Li, Kaixuan Zhao, Bo Liu, Yu Zhou
2023 J jnl
High-Efficiency Multiobjective Synchronous Modeling and Solution of Analog ICs.
Circuits Syst. Signal Process.
Bo Liu, Weizhe Zhang, Kai Li, Wenjuan Duan, Min Liu, Qingduan Meng
2022 J jnl
A precision programmable multilevel voltage output and low-temperature-variation CMOS bandgap reference with area-efficient transistor-array layout.
Integr.
Bo Liu, Pengfei Wang, Kai Li, Binrui Xu, Jincan Zhang, Liwen Zhang
2022 J jnl
Hybrid small-signal modeling of GaN HEMTs based on improved genetic algorithm.
Microelectron. J.
Jincan Zhang, Xuefeng Hou, Min Liu, Shi Yang, Bo Liu, Jinchan Wang, Juwei Zhang
2022 J jnl
IACRA: Lifetime Optimization by Invulnerability-Aware Clustering Routing Algorithm Using Game-Theoretic Approach for Wsns.
Sensors
Jun Wang, Yadan Zhang, Chunyan Hu, Pengjun Mao, Bo Liu
2022 J jnl
Large-Signal Behavior Modeling of GaN P-HEMT Based on GA-ELM Neural Network.
Circuits Syst. Signal Process.
Shaowei Wang, Jincan Zhang, Min Liu, Bo Liu, Jinchan Wang, Shi Yang
2021 J jnl
An improved GaN P-HEMT small-signal equivalent circuit with its parameter extraction.
Microelectron. J.
Jincan Zhang, Shaowei Wang, Min Liu, Bo Liu, Jinchan Wang
2019 J jnl
Density Optimization for Analog Layout Based on Transistor-Array.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Chao Geng, Bo Liu, Shigetoshi Nakatake
2019 J jnl
Design of a Low-Phase-Noise Ka-Band GaAs HBT VCO.
J. Circuits Syst. Comput.
Jincan Zhang, Min Liu, Liwen Zhang, Jinchan Wang, Bo Liu
2018 J jnl
Routable and Matched Layout Styles for Analog Module Generation.
ACM Trans. Design Autom. Electr. Syst.
Bo Liu, Gong Chen, Bo Yang, Shigetoshi Nakatake
2017 — conf
Analog Characterization Module with Data Converter-Coupled Signal Reconfiguration.
NGCAS
Daishi Isogai, Bo Liu, Yoritaka Ishiguchi, Shigetoshi Nakatake
2017 — conf
Explicit layout pattern density controlling based on transistor-array-style.
MWSCAS
Chao Geng, Bo Liu, Shigetoshi Nakatake
2017 — conf
Low Voltage Stochastic Flash ADC with Front-end of Inverter-based Comparative Unit.
ACM Great Lakes Symposium on VLSI
Xuncheng Zou, Bo Liu, Shigetoshi Nakatake
2016 J jnl
A
J. Circuits Syst. Comput.
Jincan Zhang, Yuming Zhang, Hongliang Lu, Yimen Zhang, Bo Liu, Leiming Zhang, Jinchan Wang, Liwen Zhang
2016 — conf
A multi-functional memory unit with PLA-based reconfigurable decoder.
ReConFig
Nobuyuki Yahiro, Bo Liu, Atsushi Nanri, Shigetoshi Nakatake, Yasuhiro Takashima, Gong Chen
2016 — conf
Routability of twisted common-centroid capacitor array under signal coupling constraints.
MWSCAS
Gong Chen, Bo Liu, Shigetoshi Nakatake, Bo Yang
2016 — conf
Twin-row-style for MOS analog layout.
ICECS
Bo Liu, Shigetoshi Nakatake, Bo Yang, Gong Chen
2012 — conf
CMOS op-amp circuit synthesis with geometric programming models for layout-dependent effects.
ISQED
Yu Zhang, Bo Liu, Bo Yang, Jing Li, Shigetoshi Nakatake
2012 J jnl
Layout-Aware Variability Characterization of CMOS Current Sources.
IEICE Trans. Electron.
Bo Liu, Bo Yang, Shigetoshi Nakatake
2011 — conf
Layout-aware mismatch modeling for CMOS current sources with D/A converter analysis.
ISQED
Bo Liu, Qing Dong, Bo Yang, Jing Li, Shigetoshi Nakatake
2010 — conf
D-A converter based variation analysis for analog layout design.
ASP-DAC
Bo Liu, Toru Fujimura, Bo Yang, Shigetoshi Nakatake