Bo Liu

105 papers A* 3A 5C 4Misc 2Journal 42Unranked 47
YearRankTypeTitle / Venue / Authors
2026 — conf
30.1 A 28nm 127.54TFLOPS/W MXFP6 and 117.42TFLOPS/W MXFP8 Compute-in-Memory Macro with Adaptive-Preserved-Bit-Width and Serial-Dual-Bit-Sliding Schemes.
ISSCC
Xing Wang, Yucheng Du, Tianhui Jiao, Defa Wu, Xi Chen, Miaoyu Tang, Yi Yang, Zhichao Liu, An Guo, Gaoming Fu, Peng Li, Jun Dong, Bo Liu, Xinning Liu, Weiwei Shan, Hao Cai, Guangyu Sun, Lin Tong, Jun Yang, Xin Si
2026 — conf
A 51.6μJ/Token Subspace-Rotation-Based Dual-Quantized Large-language-Model Accelerator with Fused Scale-Activation INT Datapath and Rearranged Bit-Slice LUT Computation.
ISSCC
Bo Liu, Zihan Zou, Xinming Yan, Xilong Kang, Xinyang Chen, Bo Hu, Jiaming Lin, Haoran Du, Jun Yang, Xin Si, Hao Cai
2026 J jnl
A Versatile One-Time-Programmable STT-MRAM for Security-Aware Scenario.
IEEE Trans. Reliab.
Jiongzhe Su, Haoran Du, Mingtao Chen, Keyang Zhang, Yichen Zhu, Quanhai Zhu, Bo Liu, Hao Cai
2025 — conf
14.3 A 28nm 17.83-to-62.84TFLOPS/W Broadcast-Alignment Floating-Point CIM Macro with Non-Two's-Complement MAC for CNNs and Transformers.
ISSCC
Xing Wang, Tianhui Jiao, Yi Yang, Shaochen Li, Dongqi Li, An Guo, Yuhui Shi, Yuchen Tang, Jinwu Chen, Zhican Zhang, Zhichao Liu, Bo Liu, Weiwei Shan, Xin Wang, Hao Cai, Wenwu Zhu, Jun Yang, Xin Si
2025 — conf
14.6 A 28nm 64kb Bit-Rotated Hybrid-CIM Macro with an Embedded Sign-Bit-Processing Array and a Multi-Bit-Fusion Dual-Granularity Cooperative Quantizer.
ISSCC
Xi Chen, Shaochen Li, Zhican Zhang, Wentao Zheng, Xiao Tan, Yuchen Tang, Yuhui Shi, Lizheng Ren, Yibo Mai, Feiran Liu, Jinwu Chen, Zhaoyang Zhang, An Guo, Tianzhu Xiong, Bo Wang, Xinning Liu, Weiwei Shan, Bo Liu, Hao Cai, Jun Yang, Xin Si
2025 — conf
14.7 NeuroPilot: A 28nm, 69.4fJ/node and 0.22ns/node, 32×32 Mimetic-Path-Searching CIM-Macro with Dynamic-Logic Pilot PE and Dual-Direction Searching.
ISSCC
An Guo, Jingmin Zhang, Xingyu Pu, Yi Yang, Defa Wu, Yuchen Tang, Yuhui Shi, Yinghai Gao, Zhichao Liu, Bo Wang, Tianzhu Xiong, Zhaoyang Zhang, Xi Chen, Jinwu Chen, Feiran Liu, Xing Wang, Xinning Liu, Weiwei Shan, Bo Liu, Hao Cai, Xin Si, Jun Yang
2025 — conf
A 40nm 4Mb High-Reliability STT-MRAM Achieving 18ns Write-Time and 94.9% Wafer-Level-Die-Yield Across -55°C-to-125°C.
CICC
Yaoru Hou, Haoran Du, Jiongzhe Su, Yibo Liu, Zhenghan Fang, Jia-Le Cui, Shuyu Wang, Chenxing Liu-Sun, Xuezhao Wu, Zhihua Xiao, Bo Liu, Xin Si, Jun Yang, Qiming Shao, Hao Cai
2025 — conf
A 52.03TOPS/W DCIM-Based Accelerator with FlashAttention and Sparsity-Aware Alignment for LLMs.
CICC
Bo Liu, Xingyu Xu, Yang Zhang, Xilong Kang, Qingwen Wei, Zihan Zou, Jun Yang, Hao Cai, Xin Si
2025 A conf
H3D-LLM: Heterogeneous 3D Chiplet Design for LLM Inference with Dynamic Task Scheduling and Memory-Aware Orchestration.
ICCAD
Hui Kou, Chenjie Xia, Jialin Yang, Liyi Li, Hao Cai, Xin Si, Bo Liu
2025 J jnl
KV-Cache Oriented Query-Aware Sparse Attention Accelerator With Cross-Stage Precision-Configurable Digital CIM.
IEEE Trans. Circuits Syst. II Express Briefs
Yang Zhang, Xilong Kang, Weixuan Wang, Yizhi Ding, Lizheng Ren, Yiran Zhang, Ruiqi Tan, Zhen Wang, Hao Cai, Bo Liu
2025 A* conf
OutlierCIM: Outlier-Aware Digital CIM-Based LLM Accelerator with Hybrid-Strategy Quantization and Unified FP-INT Computation.
DAC
Zihan Zou, Shikuang Chen, Chen Zhang, Xing Wang, Zhichao Liu, Haoran Du, Xin Si, Hao Cai, Bo Liu
2025 J jnl
PF²A-ViT: Parameter-Free and Feature-Aware Dynamic Token Pruning Accelerator With Complementary Quantization-Encoding for Vision Transformer.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Zihan Zou, Xinming Yan, Chen Zhang, Shikuang Chen, Guang Yang, Han Yan, Hao Cai, Bo Liu
2025 A* conf
S-DMA: Sparse Diffusion Models Acceleration via Spatiality-Aware Prediction and Dimension-Adaptive Dataflow.
MICRO
Zihan Zou, Xinming Yan, Shun Zhang, Peng Zheng, Guang Yang, Hao Cai, Bo Liu
2025 — conf
SUArch: Accelerating Layer-wise N: M Sparse Pattern with a Unified Architecture for Deep-learning Edge Device.
ASP-DAC
Xilong Kang, Qingwen Wei, Ningyuan Li, Xingyu Xu, Hao Cai, Bo Liu
2025 — conf
Serial Magnetoresistance Accumulation Supported Spiking Neural Network in STT-MRAM.
NewCAS
Xiaoyun Tian, Zhongjian Bian, Bo Liu, Xin Si, Hao Cai
2025 A conf
SparCIM: A Heterogeneous CIM-Based Accelerator for Large Language Models with Contextual and Unstructured Bit Sparsity.
ICCAD
Xingyu Xu, Yuan Song, Bo Hu, Peng Zheng, Zihan Zou, Xin Si, Bo Liu
2025 — conf
TWDP: A Vision Transformer Accelerator with Token-Weight Dual-Pruning Strategy for Edge Device Deployment.
ASP-DAC
Guang Yang, Xinming Yan, Hui Kou, Zihan Zou, Qingwen Wei, Hao Cai, Bo Liu
2024 — conf
22 nm Ultra-Low Power MCU with 43.5nW/KB Sleep Retention Power for Automotive Grade-1 Applications.
ICTA
Yibo Liu, Wen Wang, Hongjin Zhu, Longning Qi, Bo Liu, Xinning Liu, Jun Yang, Hao Cai
2024 — conf
34.3 A 22nm 64kb Lightning-Like Hybrid Computing-in-Memory Macro with a Compressed Adder Tree and Analog-Storage Quantizers for Transformer and CNNs.
ISSCC
An Guo, Xi Chen, Fangyuan Dong, Jinwu Chen, Zhihang Yuan, Xing Hu, Yuanpeng Zhang, Jingmin Zhang, Yuchen Tang, Zhican Zhang, Gang Chen, Dawei Yang, Zhaoyang Zhang, Lizheng Ren, Tianzhu Xiong, Bo Wang, Bo Liu, Weiwei Shan, Xinning Liu, Hao Cai, Guangyu Sun, Jun Yang, Xin Si
2024 — conf
A 28nm 128-kb Exponent- and Mantissa-Computation-InMemory Dual-macro for Floating-point and INT CNNs.
A-SSCC
An Guo, Xueshan Dong, Fangyuan Dong, Dongqi Li, Yiran Zhang, Jingmin Zhang, Yuchen Tang, Yuhui Shi, Xiao Tan, Bo Liu, Weiwei Shan, Hao Cai, Jun Yang, Xin Si
2024 — conf
An Index-free Coding Compression Mechanism for Vision Transformers.
ICTA
Han Yan, Zihan Zou, Shikuang Chen, Chen Zhang, Guang Yang, Hao Cai, Bo Liu
2024 — conf
Cache-Like Dual-Port SOT-MRAM with Read-while-Write Access Strategy.
ICTA
Keyang Zhang, Bo Liu, Hao Cai
2024 C conf
Complementary Series-connected STT-MTJ for Time-based Computing-in-Memory.
ISCAS
Rong Zhou, Bo Liu, Xin Si, Hao Cai
2024 A* conf
FDCA: Fine-grained Digital-CIM based CNN Accelerator with Hybrid Quantization and Weight-Stationary Dataflow.
DAC
Bo Liu, Qingwen Wei, Yang Zhang, Xingyu Xu, Zihan Zou, Xinxiang Huang, Xin Si, Hao Cai
2024 J jnl
Layer-Sensitive Neural Processing Architecture for Error-Tolerant Applications.
IEEE Trans. Very Large Scale Integr. Syst.
Zeju Li, Qinfan Wang, Zihan Zou, Qiao Shen, Na Xie, Hao Cai, Hao Zhang, Bo Liu
2024 J jnl
Layer-Wise Mixed-Modes CNN Processing Architecture With Double-Stationary Dataflow and Dimension-Reshape Strategy.
IEEE Trans. Circuits Syst. I Regul. Pap.
Bo Liu, Xinxiang Huang, Yang Zhang, Guang Yang, Han Yan, Chen Zhang, Zejv Li, Yuanhao Wang, Hao Cai
2024 C conf
Live Demonstration: A Target-Separable BWN Inspired Speech Recognition Processor with Low-power Precision-adaptive Approximate Computing.
ISCAS
Chenjie Xia, Xuanhao Zhang, Zihan Zou, Hao Cai, Bo Liu
2024 J jnl
On-Chip-Registration Supported ASR Processor Using Two-Step Transfer-Learning TWN.
IEEE Trans. Circuits Syst. II Express Briefs
Bo Liu, Xuanhao Zhang, Hui Kou, Chenjie Xia, Zhen Wang, Hao Cai
2024 Misc conf
Small-Footprint Automatic Speech Recognition System using Two-Stage Transfer Learning based Symmetrized Ternary Weight Network.
ICASSP
Xuanhao Zhang, Hui Kou, Chenjie Xia, Hao Cai, Bo Liu
2024 J jnl
Sparsity-Oriented MRAM-Centric Computing for Efficient Neural Network Inference.
IEEE Trans. Emerg. Top. Comput.
Jia-Le Cui, Yanan Guo, Juntong Chen, Bo Liu, Hao Cai
2024 J jnl
Timing Error Tolerant CNN Accelerator With Layerwise Approximate Multiplication.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Bo Liu, Na Xie, Qingwen Wei, Guang Yang, Chonghang Xie, Weiqiang Liu, Hao Cai
2024 — conf
Unveiling Security MRAM-OTP Macro using MTJ Hard Breakdown Mechanism.
AsianHOST
Jiongzhe Su, Haoran Du, Quanhai Zhu, Mingtao Chen, Keyang Zhang, Bo Liu, Hao Cai
2024 J jnl
VoAD: A Sub-μW Multiscene Voice Activity Detector Deploying Analog-Frontend Digital-Backend Circuits.
IEEE Trans. Circuits Syst. II Express Briefs
Yu Gong, Bo Liu, Hao Cai, Longxing Shi, Weiqiang Liu
2023 — conf
A 28nm 2Mb STT-MRAM Computing-in-Memory Macro with a Refined Bit-Cell and 22.4 - 41.5TOPS/W for AI Inference.
ISSCC
Hao Cai, Zhongjian Bian, Yaoru Hou, Yongliang Zhou, Jia-Le Cui, Yanan Guo, Xiaoyun Tian, Bo Liu, Xin Si, Zhen Wang, Jun Yang, Weiwei Shan
2023 J jnl
A Reconfigurable Approximate Computing Architecture With Dual-VDD for Low-Power Binarized Weight Network Deployment.
IEEE Trans. Circuits Syst. II Express Briefs
Bo Liu, Anfeng Xue, Ziyu Wang, Na Xie, Xuetao Wang, Zhen Wang, Hao Cai
2023 — conf
An Energy-Efficient MAC Design with Error Compensation Using Hybrid Approximate Logic Synthesis.
ICTA
Qingwen Wei, Yang Zhang, Xingyu Xu, Hao Cai, Bo Liu
2023 J jnl
Computing in-memory with cascaded spintronic devices for AI edge.
Comput. Electr. Eng.
Zhongjian Bian, Bo Liu, Hao Cai
2023 J jnl
Dependable STT-MRAM With Emerging Approximation and Speculation Paradigms.
IEEE Des. Test
Hao Cai, Yaoru Hou, Mengdi Zhang, Bo Liu, Lirida Alves de Barros Naviner
2023 J jnl
Multiplication Circuit Architecture for Error- Tolerant CNN-Based Keywords Speech Recognition.
IEEE Des. Test
Bo Liu, Hao Cai, Zilong Zhang, Xiaoling Ding, Renyuan Zhang, Yu Gong, Zhen Wang, Wei Ge, Jun Yang
2023 J jnl
W-AMA: Weight-aware Approximate Multiplication Architecture for neural processing.
Comput. Electr. Eng.
Bo Liu, Renyuan Zhang, Qiao Shen, Zeju Li, Na Xie, Yuanhao Wang, Chonghang Xie, Hao Cai
2023 Misc conf
Work-in-Process: Error-Compensation-Based Energy-Efficient MAC Unit for CNNs.
CASES
Xingyu Xu, Qingwen Wei, Yang Zhang, Hao Cai, Bo Liu
2022 — conf
A CGP-based Efficient Approximate Multiplier with Error Compensation.
ICTA
Qiao Shen, Renyuan Zhang, Hao Zhang, Hao Cai, Bo Liu, Jian Xiao
2022 C conf
A Low Power DNN-based Speech Recognition Processor with Precision Recoverable Approximate Computing.
ISCAS
Bo Liu, Xuetao Wang, Renyuan Zhang, Anfeng Xue, Ziyu Wang, Haige Wu, Hao Cai
2022 — conf
A TWN Inspired Speaker Verification Processor with Hardware-friendly Weight Quantization.
ICTA
Xuanhao Zhang, Haige Wu, Renyuan Zhang, Zihang Xu, Hao Zhang, Bo Liu, Hao Cai
2022 A conf
A Target-Separable BWN Inspired Speech Recognition Processor with Low-power Precision-adaptive Approximate Computing.
DATE
Bo Liu, Hao Cai, Xuan Zhang, Haige Wu, Anfeng Xue, Zilong Zhang, Zhen Wang, Jun Yang
2022 J jnl
An Efficient BCNN Deployment Method Using Quality-Aware Approximate Computing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Bo Liu, Ziyu Wang, Xuetao Wang, Renyuan Zhang, Anfeng Xue, Qiao Shen, Na Xie, Yu Gong, Zhen Wang, Jun Yang, Hao Cai
2022 — ch.
Approximate Computing for Energy-Constrained DNN-Based Speech Recognition.
Approximate Computing
Bo Liu, Hao Cai, Zhen Wang, Jun Yang
2022 J jnl
Background Noise Adaptive Energy-Efficient Keywords Recognition Processor With Reusable DNN and Reconfigurable Architecture.
IEEE Access
Guoqiang He, Xiaoling Ding, Minghao Zhou, Bo Liu, Li Li
2022 J jnl
Bit-error-rate aware sensing-error correction interaction in spintronic MRAM.
J. Syst. Archit.
Hao Cai, Xinfang Tong, Pengcheng Wu, Xinning Liu, Bo Liu
2022 J jnl
More is Less: Domain-Specific Speech Recognition Microprocessor Using One-Dimensional Convolutional Recurrent Neural Network.
IEEE Trans. Circuits Syst. I Regul. Pap.
Bo Liu, Hao Cai, Zilong Zhang, Xiaoling Ding, Ziyu Wang, Yu Gong, Weiqiang Liu, Jinjiang Yang, Zhen Wang, Jun Yang
2022 J jnl
Proposal of Analog In-Memory Computing With Magnified Tunnel Magnetoresistance Ratio and Universal STT-MRAM Cell.
IEEE Trans. Circuits Syst. I Regul. Pap.
Hao Cai, Yanan Guo, Bo Liu, Mingyang Zhou, Juntong Chen, Xinning Liu, Jun Yang
2022 J jnl
Quality Driven Systematic Approximation for Binary-Weight Neural Network Deployment.
IEEE Trans. Circuits Syst. I Regul. Pap.
Yu Gong, Hao Cai, Haige Wu, Wei Ge, Hao Yan, Zhen Wang, Longxing Shi, Bo Liu
2022 J jnl
Self-compensation tensor multiplication unit for adaptive approximate computing in low-power CNN processing.
Sci. China Inf. Sci.
Bo Liu, Zilong Zhang, Hao Cai, Reyuan Zhang, Zhen Wang, Jun Yang
2022 — ch.
Spintronic Solutions for Approximate Computing.
Approximate Computing
You Wang, Hao Cai, Kaili Zhang, Bo Wu, Bo Liu, Deming Zhang, Weisheng Zhao
2022 A conf
Triple-Skipping Near-MRAM Computing Framework for AIoT Era.
DATE
Juntong Chen, Hao Cai, Bo Liu, Jun Yang
2022 J jnl
Writing-only in-MRAM computing paradigm for ultra-low power applications.
Microprocess. Microsystems
Bo Liu, Mingyue Liu, Yongliang Zhou, Xiaofeng Hong, Hao Cai, Lirida Alves de Barros Naviner
2021 A conf
A 1D-CRNN Inspired Reconfigurable Processor for Noise-robust Low-power Keywords Recognition.
DATE
Bo Liu, Zeyu Shen, Lepeng Huang, Yu Gong, Zilong Zhang, Hao Cai
2021 J jnl
A survey of in-spin transfer torque MRAM computing.
Sci. China Inf. Sci.
Hao Cai, Bo Liu, Juntong Chen, Lirida A. B. Naviner, Yongliang Zhou, Zhen Wang, Jun Yang
2021 — conf
An Always-on Ultra-Low Power Speaker Verification Accelerator based on Binary Weighted Neural Network with System Co-optimization.
ASICON
Haige Wu, Xuan Zhang, Xiaoling Ding, Ziyu Wang, Anfeng Xue, Yu Gong, Bo Liu
2021 — conf
Cryogenic In-MRAM Computing.
NANOARCH
Yaoru Hou, We Ge, Yanan Guo, Lirida A. B. Naviner, You Wang, Bo Liu, Jun Yang, Hao Cai
2021 — conf
Implementation of a CRNN-based low-power keyword recognition system on FPGA.
ASICON
Limo Guo, Pengxu Lin, Lei Guo, Bo Liu
2021 — conf
In-MRAM Computing Elements with Single-Step Convolution and Fully Connected for BNN/TNN.
ICTA
Zhong-Jian Bian, Yanan Guo, Bo Liu, Hao Cai
2021 — conf
Low-Power Keyword Recognition Feature Extraction Circuit based on SRMFCC and Shared Multiplier for High Noise Background.
ASICON
Zilong Zhang, Haichuang Yang, Xuan Zhang, Xiaoling Ding, Xuetao Wang, Yu Gong, Bo Liu
2021 — conf
Mutual Error Compensation based Area and Power efficient Approximate Multiplier.
ASICON
Renyuan Zhang, Xuetao Wang, Ziyu Wang, Anfeng Xue, Haichuan Yang, Yu Gong, Bo Liu
2021 J jnl
Proposal of Analog In-Memory Computing with Magnified Tunnel Magnetoresistance Ratio and Universal STT-MRAM Cell.
CoRR
Hao Cai, Yanan Guo, Bo Liu, Mingyang Zhou, Juntong Chen, Xinning Liu, Jun Yang
2021 — conf
Reconfigurable Approximate Multiplication Architecture for CNN-Based Speech Recognition Using Wallace Tree Tensor Multiplier Unit.
NANOARCH
Junyi Qian, Yuanyuan Jiang, Zilong Zhang, Renyuan Zhang, Ziyu Wang, Bo Liu
2020 J jnl
A 22nm, 10.8 μ W/15.1 μ W Dual Computing Modes High Power-Performance-Area Efficiency Domained Background Noise Aware Keyword- Spotting Processor.
IEEE Trans. Circuits Syst.
Bo Liu, Hao Cai, Zhen Wang, Yuhao Sun, Zeyu Shen, Wentao Zhu, Yan Li, Yu Gong, Wei Ge, Jun Yang, Longxing Shi
2020 — conf
A Background Noise Self-adaptive VAD Using SNR Prediction Based Precision Dynamic Reconfigurable Approximate Computing.
ACM Great Lakes Symposium on VLSI
Bo Liu, Yan Li, Lepeng Huang, Hao Cai, Wentao Zhu, Shisheng Guo, Yu Gong, Zhen Wang
2020 — conf
A High-throughput Low-area Entropy Source Based on Asynchronous Feedback Unit.
ICCSP
Ping Wang, Jinjiang Yang, Min Zhu, Bo Liu
2020 J jnl
A Power Analysis Attack Countermeasure Based on Random Data Path Execution For CGRA.
IEICE Trans. Inf. Syst.
Wei Ge, Shenghua Chen, Benyu Liu, Min Zhu, Bo Liu
2020 J jnl
A Self-Timed Voltage-Mode Sensing Scheme With Successive Sensing and Checking for STT-MRAM.
IEEE Trans. Circuits Syst. I Fundam. Theory Appl.
Yongliang Zhou, Hao Cai, Lei Xie, Menglin Han, Mingyue Liu, Shi Xu, Bo Liu, Weisheng Zhao, Jun Yang
2020 — conf
An Ultra-low Power Keyword-Spotting Accelerator Using Circuit-Architecture-System Co-design and Self-adaptive Approximate Computing Based BWN.
ACM Great Lakes Symposium on VLSI
Bo Liu, Yuhao Sun, Hao Cai, Zeyu Shen, Yu Gong, Lepeng Huang, Zhen Wang
2020 C conf
Binarized Weight Neural-Network Inspired Ultra-Low Power Speech Recognition Processor with Time-Domain Based Digital-Analog Mixed Approximate Computing.
ISCAS
Bo Liu, Hao Cai, Yu Gong, Wentao Zhu, Yan Li, Wei Ge, Zhen Wang
2020 J jnl
FPGA implementation of a challenge pre-processing structure arbiter PUF designed for machine learning attack resistance.
IEICE Electron. Express
Wei Ge, Shenxin Hu, Ji Quan Huang, Bo Liu, Min Zhu
2020 J jnl
Interplay Bitwise Operation in Emerging MRAM for Efficient In-memory Computing.
CCF Trans. High Perform. Comput.
Hao Cai, Honglan Jiang, Yongliang Zhou, Menglin Han, Bo Liu
2020 J jnl
MTJ-LRB: Proposal of MTJ-Based Loop Replica Bitline as MRAM Device-Circuit Interaction for PVT-Robust Sensing.
IEEE Trans. Circuits Syst.
Yongliang Zhou, Hao Cai, Bo Liu, Weisheng Zhao, Jun Yang
2020 J jnl
QCNN Inspired Reconfigurable Keyword Spotting Processor With Hybrid Data-Weight Reuse Methods.
IEEE Access
Yu Gong, Yan Li, Xiaoling Ding, Haichuan Yang, Zilong Zhang, Xuan Zhang, Wei Ge, Zhen Wang, Bo Liu
2019 — conf
A Self-Timing Voltage-Mode Sense Amplifier for STT-MRAM Sensing Yield Improvement.
NANOARCH
Yongliang Zhou, Menglin Han, Mingyue Liu, Hao Cai, Bo Liu, Jun Yang
2019 J jnl
ARA: Cross-Layer approximate computing framework based reconfigurable architecture for CNNs.
Microelectron. J.
Yu Gong, Bo Liu, Wei Ge, Longxing Shi
2019 J jnl
An Ultra-Low Power Always-On Keyword Spotting Accelerator Using Quantized Convolutional Neural Network and Voltage-Domain Analog Switching Network-Based Approximate Computing.
IEEE Access
Bo Liu, Zhen Wang, Wentao Zhu, Yuhao Sun, Zeyu Shen, Lepeng Huang, Yan Li, Yu Gong, Wei Ge
2019 J jnl
An energy-efficient voice activity detector using deep neural networks and approximate computing.
Microelectron. J.
Bo Liu, Zhen Wang, Shisheng Guo, Huazhen Yu, Yu Gong, Jun Yang, Longxing Shi
2019 J jnl
EERA-KWS: A 163 TOPS/W Always-on Keyword Spotting Accelerator in 28nm CMOS Using Binary Weight Network and Precision Self-Adaptive Approximate Computing.
IEEE Access
Bo Liu, Zhen Wang, Hu Fan, Jing Yang, Bo Liu, Wentao Zhu, Lepeng Huang, Yu Gong, Wei Ge, Longxing Shi
2018 — conf
A Deep Learning Modeling Attack Method for MISR-APUF Protection Structures.
APCCAS
Wei Ge, Ji Quan Huang, Bo Liu, Min Zhu, Yuan Cao
2018 J jnl
A Double Dwell High Sensitivity GPS Acquisition Scheme Using Binarized Convolution Neural Network.
Sensors
Zhen Wang, Yuan Zhuang, Jun Yang, Hengfeng Zhang, Wei Dong, Min Wang, Luchi Hua, Bo Liu, Longxing Shi
2018 — conf
A Power Analysis Attack Countermeasure Based on Random Execution.
TrustCom/BigDataSE
Shenghua Chen, Wei Ge, Jinjiang Yang, Bo Liu, Jun Yang
2018 — conf
An Energy-efficient Reconfigurable Hybrid DNN Architecture for Speech Recognition with Approximate Computing.
DSP
Bo Liu, Shisheng Guo, Hai Qin, Yu Gong, Jinjiang Yang, Wei Ge, Jun Yang
2018 — conf
Design and Optimization of Reconfigurable Data Path for Communication Baseband Signal Processing.
CyberC
Shan-shan Zhu, Hai Qin, Bo Liu, Jun Yang
2018 J jnl
EERA-ASR: An Energy-Efficient Reconfigurable Architecture for Automatic Speech Recognition With Hybrid DNN and Approximate Computing.
IEEE Access
Bo Liu, Hai Qin, Yu Gong, Wei Ge, Mengwen Xia, Longxing Shi
2018 J jnl
EERA-DNN: An energy-efficient reconfigurable architecture for DNNs with hybrid bit-width and logarithmic multiplier.
IEICE Electron. Express
Zhen Wang, Mengwen Xia, Bo Liu, Xing Ruan, Yu Gong, Jinjiang Yang, Wei Ge, Jun Yang
2017 — conf
An energy-efficient accelerator for hybrid bit-width DNNs.
SSCI
Bo Liu, Xing Ruan, Mengwen Xia, Yu Gong, Jinjiang Yang, Wei Ge, Jun Yang
2017 J jnl
Coarse-grained reconfigurable architecture with hierarchical context cache structure and management approach.
IEICE Electron. Express
Chao Wang, Peng Cao, Bo Liu, Jun Yang
2017 J jnl
Context Management Scheme Optimization of Coarse-Grained Reconfigurable Architecture for Multimedia Applications.
IEEE Trans. Very Large Scale Integr. Syst.
Peng Cao, Bo Liu, Jinjiang Yang, Jun Yang, Meng Zhang, Longxing Shi
2017 J jnl
E-ERA: An energy-efficient reconfigurable architecture for RNNs using dynamically adaptive approximate computing.
IEICE Electron. Express
Bo Liu, Wei Dong, Tingting Xu, Yu Gong, Wei Ge, Jinjiang Yang, Longxing Shi
2017 — conf
Implementation and Verification of a High-Throughput Reconfigurable MIMO Detector.
CyberC
Zhen Wang, Hai Qin, Yu Gong, Bo Liu
2017 — conf
Processing LSTM in memory using hybrid network expansion model.
SiPS
Yu Gong, Tingting Xu, Bo Liu, Wei Ge, Jinjiang Yang, Jun Yang, Longxing Shi
2016 — conf
A Novel Design of Pipeline MDC-FFT Processor Based on Various Memory Access Mechanism.
CyberC
Jinjiang Yang, Dongming Zhang, Yu Gong, Bo Liu
2015 — conf
A novel configuration context cache structure of reconfigurable systems.
ASICON
Yu Gong, Bo Liu, Chen Mei, Rui-he Wang
2015 — conf
A novel routing structure of coarse-grained reconfigurable architecture for radar application.
ASICON
Bo Liu, Dongming Zhang, Wei-qi Ge, Yu Gong
2015 — conf
Performance-Conscious Reconfiguration Structure for Large-Scale Coarse-Grained Reconfigurable System.
CyberC
Bo Liu, Yu Gong, Rui-he Wang, Yang Liu
2014 — conf
A Configuration Compression Approach for Coarse-Grain Reconfigurable Architecture for Radar Signal Processing.
CyberC
Bo Liu, Wan-Yu Zhu, Yang Liu, Peng Cao
2014 — conf
Hierarchical Pipeline Optimization of Coarse Grained Reconfigurable Processor for Multimedia Applications.
IPDPS Workshops
Chen Mei, Peng Cao, Yang Zhang, Bo Liu, Leibo Liu
2012 — conf
Configuration Cache Management for Coarse-Grained Reconfigurable Architecture with Multi-Array.
CyberC
Peng Cao, Yong Cai, Bo Liu, Weiwei Shan
2012 — conf
Hybrid-Priority Configuration Cache Supervision Method for Coarse Grained Reconfigurable Architecture.
CyberC
Bo Liu, Peng Cao, Jinjiang Yang
2012 — conf
Memory Bandwidth Optimization Strategy of Coarse-Grained Reconfigurable Architecture.
CyberC
Peng Cao, Huiyan Jiang, Bo Liu, Weiwei Shan
2012 J jnl
Reconfiguration Process Optimization of Dynamically Coarse Grain Reconfigurable Architecture for Multimedia Applications.
IEICE Trans. Inf. Syst.
Bo Liu, Peng Cao, Min Zhu, Jun Yang, Leibo Liu, Shaojun Wei, Longxing Shi