Bipul Chandra Paul

21 papers A* 1A 7C 2Misc 1Journal 7Unranked 3
YearRankTypeTitle / Venue / Authors
2008 C conf
ROM based logic (RBL) design: High-performance and low-power adders.
ISCAS
Bipul Chandra Paul, Shinobu Fujita, Masaki Okajima
2007 J jnl
Negative Bias Temperature Instability: Estimation and Design for Improved Reliability of Nanoscale Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Bipul Chandra Paul, Kunhyuk Kang, Haldun Kufluoglu, Muhammad Ashraful Alam, Kaushik Roy
2006 J jnl
An Analytical Fringe Capacitance Model for Interconnects Using Conformal Mapping.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Aditya Bansal, Bipul Chandra Paul, Kaushik Roy
2006 J jnl
Low-power design techniques for scaled technologies.
Integr.
Bipul Chandra Paul, Amit Agarwal, Kaushik Roy
2006 A conf
Temporal performance degradation under NBTI: estimation and design for improved reliability of nanoscale circuits.
DATE
Bipul Chandra Paul, Kunhyuk Kang, Haldun Kufluoglu, Muhammad Ashraful Alam, Kaushik Roy
2006 A conf
Ultralow power computing with sub-threshold leakage: a comparative study of bulk and SOI technologies.
DATE
Arijit Raychowdhury, Bipul Chandra Paul, Swarup Bhunia, Kaushik Roy
2005 J jnl
A process-tolerant cache architecture for improved yield in nanoscale technologies.
IEEE Trans. Very Large Scale Integr. Syst.
Amit Agarwal, Bipul Chandra Paul, Hamid Mahmoodi-Meimand, Animesh Datta, Kaushik Roy
2005 J jnl
Computing with subthreshold leakage: device/circuit/architecture co-design for ultralow-power subthreshold operation.
IEEE Trans. Very Large Scale Integr. Syst.
Arijit Raychowdhury, Bipul Chandra Paul, Swarup Bhunia, Kaushik Roy
2005 A conf
Statistical Timing Analysis using Levelized Covariance Propagation.
DATE
Kunhyuk Kang, Bipul Chandra Paul, Kaushik Roy
2004 C conf
A Novel Fault Tolerant Cache to Improve Yield in Nanometer Technologies.
IOLTS
Amit Agarwal, Bipul Chandra Paul, Kaushik Roy
2004 — conf
Adaptive supply voltage technique for low swing interconnects.
ASP-DAC
Woopyo Jeong, Bipul Chandra Paul, Kaushik Roy
2004 A conf
Device optimization for ultra-low power digital sub-threshold operation.
ISLPED
Bipul Chandra Paul, Arijit Raychowdhury, Kaushik Roy
2004 J jnl
Enhancing Yield at the End of the Technology Roadmap.
IEEE Des. Test Comput.
Naran Sirisantana, Bipul Chandra Paul, Kaushik Roy
2004 A conf
Impact of Body Bias on Delay Fault Testing of Nanoscale CMOS Circuits.
ITC
Bipul Chandra Paul, Cassondra Neau, Kaushik Roy
2004 A* conf
Novel sizing algorithm for yield improvement under process variation in nanometer technology.
DAC
Seung Hoon Choi, Bipul Chandra Paul, Kaushik Roy
2002 — conf
Dynamic Noise Analysis with Capacitive and Inductive Coupling.
ASP-DAC/VLSI Design
Seung Hoon Choi, Bipul Chandra Paul, Kaushik Roy
2002 A conf
Testing CrossTalk Induced Delay Faults in Static CMOS Circuits Through Dynamic Timing Analysis.
ITC
Bipul Chandra Paul, Kaushik Roy
2001 — conf
Design Verification and Robust Design Technique for Cross-Talk Faults.
Asian Test Symposium
Bipul Chandra Paul, Seung Hoon Choi, Yonghee Im, Kaushik Roy
2001 J jnl
Robust subthreshold logic for ultra-low power operation.
IEEE Trans. Very Large Scale Integr. Syst.
Hendrawan Soeleman, Kaushik Roy, Bipul Chandra Paul
2001 Misc conf
Sub-Domino Logic: Ultra-Low Power Dynamic Sub-Threshold Digital Logic.
VLSI Design
Hendrawan Soeleman, Kaushik Roy, Bipul Chandra Paul
2000 A conf
Robust ultra-low power sub-threshold DTMOS logic.
ISLPED
Hendrawan Soeleman, Kaushik Roy, Bipul Chandra Paul