Bipul C. Paul

15 papers A* 1A 1Misc 1Journal 9Unranked 2
YearRankTypeTitle / Venue / Authors
2022 — conf
A Physics based MTJ Compact Model for State-of-the-Art and Emerging STT-MRAM Failure Analysis and Yield Enhancement.
IMW
Nishtha S. Gaul, Akhilesh Jaiswal, Hongsik Yoon, Taeyoung Lee, Kazutaka Yamane, Joseph Versaggi, Rick Carter, Bipul C. Paul
2019 J jnl
Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory.
IEEE Trans. Very Large Scale Integr. Syst.
Massimo Alioto, Magdy S. Abadir, Tughrul Arslan, Chirn Chye Boon, Andreas Burg, Chip-Hong Chang, Meng-Fan Chang, Yao-Wen Chang, Poki Chen, Pasquale Corsonello, Paolo Crovetti, Shiro Dosho, Rolf Drechsler, Ibrahim Abe M. Elfadel, Ruonan Han, Masanori Hashimoto, Chun-Huat Heng, Deukhyoun Heo, Tsung-Yi Ho, Houman Homayoun, Yuh-Shyan Hwang, Ajay Joshi, Rajiv V. Joshi, Tanay Karnik, Chulwoo Kim, Tony Tae-Hyoung Kim, Jaydeep P. Kulkarni, Volkan Kursun, Yoonmyung Lee, Hai Helen Li, Huawei Li, Prabhat Mishra, Baker Mohammad, Mehran Mozaffari Kermani, Makoto Nagata, Koji Nii, Partha Pratim Pande, Bipul C. Paul, Vasilis F. Pavlidis, José Pineda de Gyvez, Ioannis Savidis, Patrick Schaumont, Fabio Sebastiano, Anirban Sengupta, Mingoo Seok, Mircea R. Stan, Mark Tehranipoor, Aida Todri-Sanial, Marian Verhelst, Valerio Vignoli, Xiaoqing Wen, Jiang Xu, Wei Zhang, Zhengya Zhang, Jun Zhou, Mark Zwolinski, Stacey Weber
2018 J jnl
A Retrospective View on the Technology Evolution to Support Low Power Mobile Application.
J. Low Power Electron.
Bipul C. Paul, Ajey P. Jacob, William Taylor, Randy W. Mann, Joseph Versaggi, Edward J. Nowak, Lars W. Liebmann
2013 J jnl
Introduction to the special issue on memory technologies.
ACM J. Emerg. Technol. Comput. Syst.
Bipul C. Paul, Arijit Raychowdhury
2011 — ch.
Digital Subthreshold for Ultra-Low Power Operation: Prospects and Challenges.
Low-Power Variation-Tolerant Design in Nanometer Silicon
Bipul C. Paul, Arijit Raychowdhury
2009 J jnl
Advances in nanoelectronics circuits and systems [Editorial].
IET Comput. Digit. Tech.
Bipul C. Paul, Krishnendu Chakrabarty
2009 J jnl
ROM-Based Logic (RBL) Design: A Low-Power 16 Bit Multiplier.
IEEE J. Solid State Circuits
Bipul C. Paul, Shinobu Fujita, Masaki Okajima
2008 A conf
Optimized Circuit Failure Prediction for Aging: Practicality and Promise.
ITC
Mridul Agarwal, Varsha Balakrishnan, Anshuman Bhuyan, Kyunglok Kim, Bipul C. Paul, Wenping Wang, Bo Yang, Yu Cao, Subhasish Mitra
2007 Misc conf
Circuit Failure Prediction and Its Application to Transistor Aging.
VTS
Mridul Agarwal, Bipul C. Paul, Ming Zhang, Subhasish Mitra
2007 J jnl
Prospect of ballistic CNFET in high performance applications: Modeling and analysis.
ACM J. Emerg. Technol. Comput. Syst.
Bipul C. Paul, Shinobu Fujita, Masaki Okajima, Thomas Lee
2006 J jnl
Impact of Body Bias on Delay Fault Testing of Sub-100 nm CMOS Circuits.
J. Electron. Test.
Bipul C. Paul, Kaushik Roy
2006 A* conf
Modeling and analysis of circuit performance of ballistic CNFET.
DAC
Bipul C. Paul, Shinobu Fujita, Masaki Okajima, Thomas Lee
2006 J jnl
Statistical timing analysis using levelized covariance propagation considering systematic and random variations of process parameters.
ACM Trans. Design Autom. Electr. Syst.
Kunhyuk Kang, Bipul C. Paul, Kaushik Roy
2005 J jnl
Process variation in embedded memories: failure analysis and variation aware architecture.
IEEE J. Solid State Circuits
Amit Agarwal, Bipul C. Paul, Saibal Mukhopadhyay, Kaushik Roy
2004 — conf
Process variation in nano-scale memories: failure analysis and process tolerant architecture.
CICC
Amit Agarwal, Bipul C. Paul, Kaushik Roy