Binsu J. Kailath

22 papers A* 1A 1Misc 2Journal 7Unranked 11

Year	Rank	Type	Title / Venue / Authors
2026	Misc	`conf`	Spike-Based Time-Domain ECG Wave Delineation for Low-Power VLSI Implementation. VLSID Priya K, Binsu J. Kailath
2025	Misc	`conf`	Atrial Flutter Detection System by AdEx Encoded Lead-II ECG. VLSID Sushmi R, Priya K, Binsu J. Kailath
2025	—	`conf`	Hardware-Efficient Rwave Delineation by AdEx Encoded Lead II ECG: No Filters, No Preprocessing. PRIME Priya K, Binsu J. Kailath
2025	A*	`conf`	Late Breaking Results: Versatile 4:1 Multiplexer Using 1T1R RRAM Crossbar for High Speed In-Memory Computing. DAC B. Vinodh Kumar, Binsu J. Kailath
2025	J	`jnl`	SleepISI: A Neuromorphic Time-Domain EEG Classification Framework Using Inter-Spike Intervals From AdEx Encoding of C4-A1 Signals. IEEE J. Biomed. Health Informatics Asha V, Vasanthi R, Sapna E. Sreedharan, Kalpana Settu, Binsu J. Kailath
2024	A	`conf`	CiMComp: An Energy Efficient Compute-in-Memory Based Comparator for Convolutional Neural Networks. DATE Kavitha S, Binsu J. Kailath, Bhupendra Singh Reniwal
2024	J	`jnl`	Development of Accurate Model for Memristor-Based Filters and Oscillators: Amplitude, Frequency and Ramp-Rate Dependent Analysis. IEEE Trans. Circuits Syst. II Express Briefs Rami Reddy Sowmya, Arige Sumanth, Binsu J. Kailath, Tejendra Dixit
2024	—	`conf`	SNN with Gradient-based Backpropagation algorithm for ECG arrhythmia classification with LIF neuron and AdEx neuron. VDAT Bana Shanmuga Sai Badrinatha Reddy, Priya K, Binsu J. Kailath
2022	J	`jnl`	Graph-Based Circuit Simulator for Switched Capacitor Circuits. IEEE Des. Test Dinesh Ganesan, Binsu J. Kailath
2021	—	`conf`	A Novel Biphasic Neuron Encoder Implementation. AIIoT Madhuvanthi Srivatsav R, Binsu J. Kailath
2021	—	`conf`	Bistable-Triplet STDP circuit without external memory for Integrating with Silicon Neurons. AIIoT Sathiya Jothi. S, Binsu J. Kailath
2021	J	`jnl`	High speed Power efficient Vedic arithmetic modules on Zedboard-Zynq-7000 FPGA. Int. J. Circuit Theory Appl. Sujitha S, Binsu J. Kailath
2021	J	`jnl`	Tree/link method for transfer function and stability analysis of switched-capacitor circuits. Int. J. Circuit Theory Appl. Dinesh Ganesan, Binsu J. Kailath
2020	—	`conf`	A Silicon Neuron-based Bio-Front-End for Ultra Low Power Bio-Monitoring at the Edge. SSCI T. P. Shivangi, M. Rahimi, Gaetano D. Gargiulo, Binsu J. Kailath, Tara Julia Hamilton
2020	—	`conf`	Reusable Spiking Neural Network Architecture. UEMCON Sai G. Pavan, Binsu J. Kailath
2019	—	`conf`	FPGA Implementation of Speech Recognizer for Isolated Words. iSES Nithya K, Muralidhar Gadamsetty, Binsu J. Kailath
2018	J	`jnl`	PLL architecture with a composite PFD and variable loop filter. IET Circuits Devices Syst. Abdul Majeed Kottampara Kuppalath, Binsu J. Kailath
2017	—	`conf`	Realization of Multiplier Using Delay Efficient Cyclic Redundant Adder. VDAT K. Dheepika, K. S. Jevasankari, Vippin Chandhar, Binsu J. Kailath
2016	—	`conf`	Improved alias rejection using interleaved CIC decimation filter. NEWCAS S. S. Karthikeyan, Dinesh Ganesan, Binsu J. Kailath
2016	J	`jnl`	Nonlinear PFD free of glitches and blind zone for a fast locking PLL with reduced reference spur. IEICE Electron. Express Abdul Majeed Kottampara Kuppalath, Binsu J. Kailath
2016	—	`conf`	QSCsim - Charge Based Switched Capacitor Simulator. iNIS Binsu J. Kailath, Dinesh Ganesan
2016	—	`conf`	Switched-capacitor circuit simulator in Q-V domain including nonidealities. VDAT G. Muralidhar, Dinesh Ganesan, Binsu J. Kailath