Binod Kumar - RankMe

48 papers C 3Misc 6Journal 13Unranked 26

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	FPGA-Based Medical Image Processing Using Hardware-Software Co-Design Approach. IEEE Trans. Biomed. Circuits Syst. Abhishek Yadav, Vyom Kumar Gupta, Binod Kumar
2025	J	`jnl`	Lightweight Surveillance Image Classification Through Hardware-Software Co-Design. IEEE Embed. Syst. Lett. Abhishek Yadav, Vyom Kumar Gupta, Binod Kumar
2025	Misc	`conf`	Multi-Object Detection Through Meta-Training in Resource-Constrained UAV-Based Surveillance Applications. VLSID Abhishek Yadav, Vyom Kumar Gupta, Kethireddy Harshith Reddy, Masahiro Fujita, Binod Kumar
2025	J	`jnl`	On-Chip Implementation of Neural Network-Based Classifier Models for E-Nose With Chemometric Analysis. IEEE Trans. Instrum. Meas. Vyom Kumar Gupta, Abhishek Yadav, Mirgender Kumar, Binod Kumar, Sunny
2025	—	`conf`	Resource-Efficient LSTM Architecture for Keyword Spotting with CORDIC-Activation Approximation. ISVLSI Abhishek Yadav, Ayush Dixit, Utsav Jana, Masahiro Fujita, Binod Kumar
2025	J	`jnl`	Variational inference-aided neural architecture search for secure deep learning implementation. Neurocomputing Abhishek Yadav, Vyom Kumar Gupta, Gaurav Singh Bhati, Binod Kumar
2024	—	`conf`	A Reconfigurable Floating-Point Compliant Hardware Architecture for Neural Network Implementation. iSES Abhishek Yadav, Ayush Dixit, Utsav Jana, Binod Kumar
2024	—	`conf`	Harnessing Knowledge-Distillation for Lightweight AI-Implementation on Resource-Constrained Device. iSES Abhishek Yadav, Vyom Kumar Gupta, Binod Kumar
2024	—	`conf`	LLM-aided Front-End Design Framework For Early Development of Verified RTLs. ATS Vyom Kumar Gupta, Abhishek Yadav, Masahiro Fujita, Binod Kumar
2024	—	`conf`	Lightweight DL-based Drone Image Classification for Surveillance Applications. ISOCC Abhishek Yadav, Masahiro Fujita, Binod Kumar
2024	—	`conf`	MEMFD: A Multi-EDT Multi-Fault Scan Chain Diagnosis Methodology with Deep Learning. ATS Saman Aijaz Siddiqui, Uzair Ruhulamin Patel, Utsav Jana, Binod Kumar
2024	—	`conf`	Resource-efficient DL Model Inference with Weight Clustering and Zero-skipping. ISOCC Abhishek Yadav, Masahiro Fujita, Binod Kumar
2023	—	`conf`	A Case Study on Formally Verifying an Open-source Deep Learning Accelerator Design. ATS Anshul Jain, Binod Kumar
2022	J	`jnl`	Aries: A Semiformal Technique for Fine-Grained Bug Localization in Hardware Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Binod Kumar, V. S. Vineesh, Puneet Nemade, Masahiro Fujita
2022	—	`conf`	Blood Pressure Estimation from ECG Data Using XGBoost and ANN for Wearable Devices. ICECS 2022 Sourav Banerjee, Binod Kumar, Alex P. James, Jai Narayan Tripathi
2022	—	`conf`	Deep Learning-assisted Scan Chain Diagnosis with Different Fault Models during Manufacturing Test. ATS Utsav Jana, Sourav Banerjee, Binod Kumar, Madhu B, Shankar Umapathi, Masahiro Fujita
2022	C	`conf`	Hardware Accelerator Design for Healthcare Applications: Review and Perspectives. ISCAS Jai Narayan Tripathi, Binod Kumar, Dinesh Junjariya
2021	J	`jnl`	Enhanced Design Debugging With Assistance From Guidance-Based Model Checking. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. V. S. Vineesh, Binod Kumar, Rushikesh Shinde, Neelam Sharma, Masahiro Fujita, Virendra Singh
2021	—	`conf`	Enhancing Testbench Quality via Genetic Algorithm. MWSCAS Harsh Bhargav, Vineesh V. S., Binod Kumar, Virendra Singh
2020	Misc	`conf`	A Low Overhead Methodology for Validating Memory Consistency Models in Chip Multiprocessors. VLSID Binod Kumar, Swapniel Thakur, Kanad Basu, Masahiro Fujita, Virendra Singh
2020	J	`jnl`	A Methodology to Capture Fine-Grained Internal Visibility During Multisession Silicon Debug. IEEE Trans. Very Large Scale Integr. Syst. Binod Kumar, Jay Adhaduk, Kanad Basu, Masahiro Fujita, Virendra Singh
2020	Misc	`conf`	Analyzing Hardware Security Properties of Processors through Model Checking. VLSID Binod Kumar, Akshay Kumar Jaiswal, V. S. Vineesh, Rushikesh Shinde
2020	J	`jnl`	DeepPeep: Exploiting Design Ramifications to Decipher the Architecture of Compact DNNs. CoRR Nandan Kumar Jha, Sparsh Mittal, Binod Kumar, Govardhan Mattela
2020	J	`jnl`	DeepPeep: Exploiting Design Ramifications to Decipher the Architecture of Compact DNNs. ACM J. Emerg. Technol. Comput. Syst. Nandan Kumar Jha, Sparsh Mittal, Binod Kumar, Govardhan Mattela
2020	J	`jnl`	Post-Silicon Gate-Level Error Localization With Effective and Combined Trace Signal Selection. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Binod Kumar, Kanad Basu, Masahiro Fujita, Virendra Singh
2019	Misc	`conf`	A Methodology for SAT-Based Electrical Error Debugging During Post-Silicon Validation. VLSID Binod Kumar, Masahiro Fujita, Virendra Singh
2019	—	`conf`	A Unified Methodology for Hardware Obfuscation and IP Watermarking. VDAT Saurabh Gangurde, Binod Kumar
2019	—	`conf`	Identification of Effective Guidance Hints for Better Design Debugging by Formal Methods. VDAT V. S. Vineesh, Binod Kumar, Jay Adhaduk
2019	—	`conf`	Orion: A Technique to Prune State Space Search Directions for Guidance-Based Formal Verification. ATS Vineesh V. S., Binod Kumar, Rushikesh Shinde, Akshay Jaiswal, Harsh Bhargava, Virendra Singh
2019	J	`jnl`	Power-Delay-Error-Efficient Approximate Adder for Error-Resilient Applications. J. Circuits Syst. Comput. Vinay Kumar, Ankit Singh, Shubham Upadhyay, Binod Kumar
2019	J	`jnl`	SAT-based Silicon Debug of Electrical Errors under Restricted Observability Enhancement. J. Electron. Test. Binod Kumar, Masahiro Fujita, Virendra Singh
2019	—	`conf`	Validating Multi-Processor Cache Coherence Mechanisms under Diminished Observability. ATS Binod Kumar, Atul Kumar Bhosale, Masahiro Fujita, Virendra Singh
2018	—	`conf`	A Technique for Electrical Error Localization with Learning Methods During Post-silicon Debugging. IGSC Binod Kumar, Kanad Basu, Virendra Singh
2018	Misc	`conf`	ELURA: A Methodology for Post-Silicon Gate-Level Error Localization Using Regression Analysis. VLSID Ankit Jindal, Binod Kumar, Kanad Basu, Masahiro Fujita
2018	—	`conf`	Silicon Debug with Maximally Expanded Internal Observability Using Nearest Neighbor Algorithm. ISVLSI Ankit Jindal, Binod Kumar, Nitish Jindal, Masahiro Fujita, Virendra Singh
2017	—	`conf`	A Formal Perspective on Effective Post-silicon Debug and Trace Signal Selection. VDAT Binod Kumar, Kanad Basu, Ankit Jindal, Brajesh Pandey, Masahiro Fujita
2017	Misc	`conf`	A Methodology for Trace Signal Selection to Improve Error Detection in Post-Silicon Validation. VLSID Binod Kumar, Ankit Jindal, Virendra Singh, Masahiro Fujita
2017	J	`jnl`	A Novel Shared Active Pixel Architecture (SAPA) with Low Dark Current and High Fill-Factor (FF) for CMOS Image Sensors. J. Low Power Electron. Vinay Kumar, Krishna Lal Baishnab, Binod Kumar
2017	—	`conf`	Combining Restorability and Error Detection Ability for Effective Trace Signal Selection. ACM Great Lakes Symposium on VLSI Binod Kumar, Ankit Jindal, Masahiro Fujita, Virendra Singh
2017	C	`conf`	Improving post-silicon error detection with topological selection of trace signals. VLSI-SoC Binod Kumar, Kanad Basu, Ankit Jindal, Masahiro Fujita, Virendra Singh
2017	—	`conf`	Post-silicon observability enhancement with topology based trace signal selection. LATS Binod Kumar, Ankit Jindal, Masahiro Fujita, Virendra Singh
2017	—	`conf`	RTL level trace signal selection and coverage estimation during post-silicon validation. HLDVT Binod Kumar, Kanad Basu, Masahiro Fujita, Virendra Singh
2017	C	`conf`	Revisiting random access scan for effective enhancement of post-silicon observability. IOLTS Binod Kumar, Ankit Jindal, Jaynarayan T. Tudu, Brajesh Pandey, Virendra Singh
2017	—	`conf`	Testing multiple stuck-at faults of ROBDD based combinational circuit design. LATS Toral Shah, Anzhela Yu. Matrosova, Binod Kumar, Masahiro Fujita, Virendra Singh
2016	—	`conf`	A technique for low power, stuck-at fault diagnosable and reconfigurable scan architecture. EWDTS Binod Kumar, Boda Nehru, Brajesh Pandey, Virendra Singh, Jaynarayan T. Tudu
2016	—	`conf`	A trace signal selection algorithm for improved post-silicon debug. EWDTS Binod Kumar, Ankit Jindal, Virendra Singh
2016	—	`conf`	Performance modelling of heterogeneous ISA multicore architectures. EWDTS Nirmal Kumar Boran, Rameshwar Prasad Meghwal, Kuldeep Sharma, Binod Kumar, Virendra Singh
2016	—	`conf`	Skip-scan: A methodology for test time reduction. VDAT Binod Kumar, Boda Nehru, Brajesh Pandey, Jaynarayan T. Tudu