Bingyi Ye

17 papers C 3Journal 4Unranked 10
YearRankTypeTitle / Venue / Authors
2026 — conf
8.4 A 112Gb/S/Wire Single-Ended Simultaneous Bi-Directional Transceiver with Dynamic Equalizer for Die-to-Die Interface in 28nm CMOS.
ISSCC
Zhiwen Huang, Zhifei Wang, Bingyi Ye, Tianchen Ye, Dunshan Yu, Wei Wang, Weixin Gai
2025 — conf
25.5 A 99.5mW/Port DC-to-40GHz Integrated Channel Analyzer for High-Density Signal Integrity Measurement in 28nm CMOS.
ISSCC
Guangdong Wu, Yuanliang Li, Bingyi Ye, Fangzhu Li, Xin Liu, Haowei Niu, Ruixu Wang, Dunshan Yu, Weixin Gai
2025 — conf
A 1.11pJ/b 224Gb/s XSR Receiver with Slice-Based CTLE and PI-Based Clock Generator in 12nm CMOS.
ISSCC
Bingyi Ye, Tianchen Ye, Tianyuan Zhong, Zhiwen Huang, Lei Shen, Boyang Zhang, Dunshan Yu, Yandong He, Weixin Gai
2025 — conf
A 50Gb/s Burst-Mode NRZ Receiver with 5-Tap FFE, 7-Tap DFE and 15ns Lock Time in 28nm CMOS for Symmetric 50G-PON.
ISSCC
Boyang Zhang, Tianchen Ye, Shuaizhe Ma, Tianyuan Zhong, Xin Liu, Feiyang Zhang, Bingyi Ye, Dan Li, Weixin Gai
2025 — conf
A 64Gb/s/wire 10.5Tb/s/mm/Layer Single-Ended Simultaneous Bi-Directional Transceiver with Echo and Crosstalk Cancellation for a Die-to-Die Interface in 28nm CMOS.
ISSCC
Zhifei Wang, Zhiwen Huang, Tianchen Ye, Bingyi Ye, Fangzhu Li, Wei Wang, Dunshan Yu, Weixin Gai
2024 — conf
A 200-Gb/s PAM-4 Transmitter with 1.6-Vppd Output Swing and Clock Skew Correction in 12-nm FinFET.
VLSI Technology and Circuits
Boyang Zhang, Zhifei Wang, Zeze Feng, Tianchen Ye, Bingyi Ye, Zixu Wang, Weixin Gai
2024 J jnl
A Five-Tap Delay-Line-Based Feed-Forward-Equalizer for 200-Gb/s Wireline Receiver in 28-nm CMOS.
IEEE J. Solid State Circuits
Bingyi Ye, Guangdong Wu, Weixin Gai, Kai Sheng, Yandong He
2023 — conf
A 0.43pJ/b 200Gb/s 5-Tap Delay-Line-Based Receiver FFE with Low-Frequency Equalization in 28nm CMOS.
ISSCC
Bingyi Ye, Guangdong Wu, Weixin Gai, Kai Sheng, Yandong He
2023 — conf
A 128Gb/s PAM-4 Transmitter with Programmable-Width Pulse Generator and Pattern-Dependent Pre-Emphasis in 28nm CMOS.
ISSCC
Kai Sheng, Weixin Gai, Zeze Feng, Haowei Niu, Bingyi Ye, Hang Zhou
2023 J jnl
A 2.29-pJ/b 112-Gb/s Wireline Transceiver With RX Four-Tap FFE for Medium-Reach Applications in 28-nm CMOS.
IEEE J. Solid State Circuits
Bingyi Ye, Kai Sheng, Weixin Gai, Haowei Niu, Boyang Zhang, Yandong He, Song Jia, Congcong Chen, Jiaqi Yu
2023 J jnl
A 4.6-pJ/b 200-Gb/s Analog DP-QPSK Coherent Optical Receiver in 28-nm CMOS.
IEEE J. Solid State Circuits
Kai Sheng, Haowei Niu, Boyang Zhang, Weixin Gai, Bingyi Ye, Hang Zhou, Congcong Chen
2022 — conf
A 2.29pJ/b 112Gb/s Wireline Transceiver with RX 4-Tap FFE for Medium-Reach Applications in 28nm CMOS.
ISSCC
Bingyi Ye, Kai Sheng, Weixin Gai, Haowei Niu, Boyang Zhang, Yandong He, Song Jia, Congcong Chen, Jiaqi Yu
2022 — conf
A 4.6pJ/b 200Gb/s Analog DP-QPSK Coherent Optical Receiver in 28nm CMOS.
ISSCC
Kai Sheng, Haowei Niu, Boyang Zhang, Weixin Gai, Bingyi Ye, Hang Zhou, Congcong Chen
2022 C conf
A High-Linearity 14GHz 7b Phase Interpolator for Ultra-High-Speed Wireline Applications.
ISCAS
Ninghuang Li, Weixin Gai, Bingyi Ye, Haowei Niu, Lei Lu
2021 J jnl
56 Gb/s PAM4 receiver with an overshoot compensation scheme in 28 nm CMOS technology.
Microelectron. J.
Ai He, Weixin Gai, Bingyi Ye, Boyang Zhang, Kai Sheng, Yuanliang Li
2021 C conf
A 25Gb/s 185mW PAM-4 Receiver with 4-Tap Adaptive DFE and Sampling Clock Optimization in 55nm CMOS.
ISCAS
Liangxiao Tang, Weixin Gai, Chih-Kong Ken Yang, Bingyi Ye, Congcong Chen
2021 C conf
Analog Signal Processing Circuits for a 400Gb/s 16QAM Optical Coherent Receiver.
ISCAS
Boyang Zhang, Weixin Gai, Haowei Niu, Bingyi Ye, Kai Sheng, Tianjian Zuo, Lei Liu