Bingfeng Mei - RankMe

17 papers A 3B 5Misc 1Journal 5Unranked 3

Year	Rank	Type	Title / Venue / Authors
2010	J	`jnl`	An Efficient Memory Organization for High-ILP Inner Modem Baseband SDR Processors. J. Signal Process. Syst. Bjorn De Sutter, Osman Allam, Praveen Raghavan, Roeland Vandebriel, Hans Cappelle, Tom Vander Aa, Bingfeng Mei
2009	J	`jnl`	Interconnect Exploration for Energy Versus Performance Tradeoffs for Coarse Grained Reconfigurable Architectures. IEEE Trans. Very Large Scale Integr. Syst. Andy Lambrechts, Praveen Raghavan, Murali Jayapala, Bingfeng Mei, Francky Catthoor, Diederik Verkest
2009	J	`jnl`	Mapping of nomadic multimedia applications on the ADRES reconfigurable array processor. Microprocess. Microsystems Mladen Berekovic, Andreas Kanstein, Bingfeng Mei, Bjorn De Sutter
2008	J	`jnl`	Implementation of a Coarse-Grained Reconfigurable Media Processor for AVC Decoder. J. Signal Process. Syst. Bingfeng Mei, Bjorn De Sutter, Tom Vander Aa, M. Wouters, Andreas Kanstein, Steven Dupont
2008	B	`conf`	Placement-and-routing-based register allocation for coarse-grained reconfigurable arrays. LCTES Bjorn De Sutter, Paul Coene, Tom Vander Aa, Bingfeng Mei
2007	Misc	`conf`	A backtracking instruction scheduler using predicate-based code hoisting to fill delay slots. CASES Tom Vander Aa, Bingfeng Mei, Bjorn De Sutter
2006	—	`conf`	Hardware and a Tool Chain for ADRES. ARC Bjorn De Sutter, Bingfeng Mei, T. Andrei Bartic, Tom Vander Aa, Mladen Berekovic, Jean-Yves Mignolet, Kris Croes, Paul Coene, Miro Cupac, Aïssa Couvreur, Andy Folens, Steven Dupont, Bert Van Thielen, Andreas Kanstein, Hong-Seok Kim, Sukjin Kim
2005	J	`jnl`	Architecture Exploration for a Reconfigurable Architecture Template. IEEE Des. Test Comput. Bingfeng Mei, Andy Lambrechts, Diederik Verkest, Jean-Yves Mignolet, Rudy Lauwereins
2005	B	`conf`	Custom Implementation of the Coarse-Grained Reconfigurable ADRES Architecture for Multimedia Purposes. FPL Francisco-Javier Veredas, Michael Scheppler, Will Moffat, Bingfeng Mei
2005	B	`conf`	Mapping an H.264/AVC Decoder onto the ADRES Reconfigurable Architecture. FPL Bingfeng Mei, Francisco-Javier Veredas, Bart Masschelein
2004	A	`conf`	Design Methodology for a Tightly Coupled VLIW/Reconfigurable Matrix Architecture: A Case Study. DATE Bingfeng Mei, Serge Vernalde, Diederik Verkest, Rudy Lauwereins
2004	A	`conf`	Design Style Case Study for Embedded Multi Media Compute Nodes. RTSS Andy Lambrechts, Tom Vander Aa, Murali Jayapala, Guillermo Talavera, Anthony Leroy, Adelina Shickova, Francisco Barat, Bingfeng Mei, Francky Catthoor, Diederik Verkest, Geert Deconinck, Henk Corporaal, Frédéric Robert, Jordi Carrabina Bordoll
2004	—	`conf`	Interconnect architectures for modulo-scheduled coarse-grained reconfigurable arrays. FPT Steven J. E. Wilton, Noha Kafafi, Bingfeng Mei, Serge Vernalde
2003	B	`conf`	ADRES: An Architecture with Tightly Coupled VLIW Processor and Coarse-Grained Reconfigurable Matrix. FPL Bingfeng Mei, Serge Vernalde, Diederik Verkest, Hugo De Man, Rudy Lauwereins
2003	A	`conf`	Exploiting Loop-Level Parallelism on Coarse-Grained Reconfigurable Architectures Using Modulo Scheduling. DATE Bingfeng Mei, Serge Vernalde, Diederik Verkest, Hugo De Man, Rudy Lauwereins
2002	—	`conf`	DRESC: a retargetable compiler for coarse-grained reconfigurable architectures. FPT Bingfeng Mei, Serge Vernalde, Diederik Verkest, Hugo De Man, Rudy Lauwereins
2001	B	`conf`	Development of a Design Framework for Platform-Independent Networked Reconfiguration of Software and Hardware. FPL Yajun Ha, Bingfeng Mei, Patrick Schaumont, Serge Vernalde, Rudy Lauwereins, Hugo De Man