Bing Li - RankMe

176 papers A* 15A 41B 2C 3Journal 84Unranked 31

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	HLSRewriter: Efficient Refactoring and Optimization of C/C++ Code with LLMs for High-Level Synthesis. ACM Trans. Design Autom. Electr. Syst. Kangwei Xu, Grace Li Zhang, Xunzhao Yin, Cheng Zhuo, Ulf Schlichtmann, Bing Li
2026	J	`jnl`	Late Breaking Results: Conversion of Neural Networks into Logic Flows for Edge Computing. CoRR Daniel Stein, Shaoyi Huang, Rolf Drechsler, Bing Li, Grace Li Zhang
2026	J	`jnl`	OptINC: Optical In-Network-Computing for Scalable Distributed Learning. CoRR Sijie Fei, Grace Li Zhang, Bing Li, Ulf Schlichtmann
2025	J	`jnl`	A Scalable 2T-1FeFET-Based Content Addressable Memory Design for Energy Efficient Data Search. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jiahao Cai, Hamza Errahmouni Barkam, Mohsen Imani, Kai Ni, Grace Li Zhang, Bing Li, Ulf Schlichtmann, Cheng Zhuo, Xunzhao Yin
2025	—	`conf`	An Efficient General-Purpose Optical Accelerator for Neural Networks. ASP-DAC Sijie Fei, Amro Eldebiky, Grace Li Zhang, Bing Li, Ulf Schlichtmann
2025	A*	`conf`	Basis Sharing: Cross-Layer Parameter Sharing for Large Language Model Compression. ICLR Jingcun Wang, Yu-Guang Chen, Ing-Chao Lin, Bing Li, Grace Li Zhang
2025	J	`jnl`	CompressKV: Semantic Retrieval Heads Know What Tokens are Not Important Before Generation. CoRR Xiaolin Lin, Jingcun Wang, Olga Kondrateva, Yiyu Shi, Bing Li, Grace Li Zhang
2025	A	`conf`	CorrectBench: Automatic Testbench Generation with Functional Self-Correction using LLMs for HDL Design. DATE Ruidi Qiu, Grace Li Zhang, Rolf Drechsler, Ulf Schlichtmann, Bing Li
2025	J	`jnl`	CorrectHDL: Agentic HDL Design with LLMs Leveraging High-Level Synthesis as Reference. CoRR Kangwei Xu, Grace Li Zhang, Ulf Schlichtmann, Bing Li
2025	J	`jnl`	Efficient Model Switching in RRAM-Based DNN Accelerators. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Fang-Yi Gu, Ing-Chao Lin, Bing Li, Ulf Schlichtmann, Grace Li Zhang
2025	A	`conf`	HLSTester: Efficient Testing of Behavioral Discrepancies with LLMs for High-Level Synthesis. ICCAD Kangwei Xu, Bing Li, Grace Li Zhang, Ulf Schlichtmann
2025	J	`jnl`	HLSTester: Efficient Testing of Behavioral Discrepancies with LLMs for High-Level Synthesis. CoRR Kangwei Xu, Bing Li, Grace Li Zhang, Ulf Schlichtmann
2025	—	`conf`	Large Language Models (LLMs) for Electronic Design Automation (EDA) : Special Session Paper. SOCC Kangwei Xu, Denis Schwachhofer, Jason Blocklove, Ilia Polian, Peter Domanski, Dirk Pflüger, Siddharth Garg, Ramesh Karri, Ozgur Sinanoglu, Johann Knechtel, Zhuorui Zhao, Ulf Schlichtmann, Bing Li
2025	J	`jnl`	Large Language Models (LLMs) for Electronic Design Automation (EDA). CoRR Kangwei Xu, Denis Schwachhofer, Jason Blocklove, Ilia Polian, Peter Domanski, Dirk Pflüger, Siddharth Garg, Ramesh Karri, Ozgur Sinanoglu, Johann Knechtel, Zhuorui Zhao, Ulf Schlichtmann, Bing Li
2025	B	`conf`	Large Language Models (LLMs) for Verification, Testing, and Design. ETS Chandan Kumar Jha, Muhammad Hassan, Khushboo Qayyum, Sallar Ahmadi-Pour, Kangwei Xu, Ruidi Qiu, Jason Blocklove, Luca Collini, Andre Nakkab, Ulf Schlichtmann, Grace Li Zhang, Ramesh Karri, Bing Li, Siddharth Garg, Rolf Drechsler
2025	—	`conf`	Paradigm-Based Automatic HDL Code Generation Using LLMs. ISQED Wenhao Sun, Bing Li, Grace Li Zhang, Xunzhao Yin, Cheng Zhuo, Ulf Schlichtmann
2025	J	`jnl`	Paradigm-Based Automatic HDL Code Generation Using LLMs. CoRR Wenhao Sun, Bing Li, Grace Li Zhang, Xunzhao Yin, Cheng Zhuo, Ulf Schlichtmann
2025	—	`conf`	VFocus: Better Verilog Generation from Large Language Model via Focused Reasoning. SOCC Zhuorui Zhao, Bing Li, Grace Li Zhang, Ulf Schlichtmann
2025	J	`jnl`	VFocus: Better Verilog Generation from Large Language Model via Focused Reasoning. CoRR Zhuorui Zhao, Bing Li, Grace Li Zhang, Ulf Schlichtmann
2025	—	`conf`	VRank: Enhancing Verilog Code Generation from Large Language Models via Self-Consistency. ISQED Zhuorui Zhao, Ruidi Qiu, Ing-Chao Lin, Grace Li Zhang, Bing Li, Ulf Schlichtmann
2025	J	`jnl`	VRank: Enhancing Verilog Code Generation from Large Language Models via Self-Consistency. CoRR Zhuorui Zhao, Ruidi Qiu, Ing-Chao Lin, Grace Li Zhang, Bing Li, Ulf Schlichtmann
2024	A	`conf`	A FeFET-based Time-Domain Associative Memory for Multi-bit Similarity Computation. DATE Qingrong Huang, Hamza Errahmouni Barkam, Zeyu Yang, Jianyi Yang, Thomas Kämpfe, Kai Ni, Grace Li Zhang, Bing Li, Ulf Schlichtmann, Mohsen Imani, Cheng Zhuo, Xunzhao Yin
2024	J	`jnl`	An Efficient General-Purpose Optical Accelerator for Neural Networks. CoRR Sijie Fei, Amro Eldebiky, Grace Li Zhang, Bing Li, Ulf Schlichtmann
2024	—	`conf`	AutoBench: Automatic Testbench Generation and Evaluation Using LLMs for HDL Design. MLCAD Ruidi Qiu, Grace Li Zhang, Rolf Drechsler, Ulf Schlichtmann, Bing Li
2024	J	`jnl`	AutoBench: Automatic Testbench Generation and Evaluation Using LLMs for HDL Design. CoRR Ruidi Qiu, Grace Li Zhang, Rolf Drechsler, Ulf Schlichtmann, Bing Li
2024	—	`conf`	Automated C/C++ Program Repair for High-Level Synthesis via Large Language Models. MLCAD Kangwei Xu, Grace Li Zhang, Xunzhao Yin, Cheng Zhuo, Ulf Schlichtmann, Bing Li
2024	J	`jnl`	Automated C/C++ Program Repair for High-Level Synthesis via Large Language Models. CoRR Kangwei Xu, Grace Li Zhang, Xunzhao Yin, Cheng Zhuo, Ulf Schlichtmann, Bing Li
2024	J	`jnl`	Basis Sharing: Cross-Layer Parameter Sharing for Large Language Model Compression. CoRR Jingcun Wang, Yu-Guang Chen, Ing-Chao Lin, Bing Li, Grace Li Zhang
2024	A	`conf`	BasisN: Reprogramming-Free RRAM-Based In-Memory-Computing by Basis Combination for Deep Neural Networks. ICCAD Amro Eldebiky, Grace Li Zhang, Xunzhao Yin, Cheng Zhuo, Ing-Chao Lin, Ulf Schlichtmann, Bing Li
2024	J	`jnl`	BasisN: Reprogramming-Free RRAM-Based In-Memory-Computing by Basis Combination for Deep Neural Networks. CoRR Amro Eldebiky, Grace Li Zhang, Xunzhao Yin, Cheng Zhuo, Ing-Chao Lin, Ulf Schlichtmann, Bing Li
2024	J	`jnl`	Classification-Based Automatic HDL Code Generation Using LLMs. CoRR Wenhao Sun, Bing Li, Grace Li Zhang, Xunzhao Yin, Cheng Zhuo, Ulf Schlichtmann
2024	A	`conf`	Computational and Storage Efficient Quadratic Neurons for Deep Neural Networks. DATE Chuangtao Chen, Grace Li Zhang, Xunzhao Yin, Cheng Zhuo, Ulf Schlichtmann, Bing Li
2024	J	`jnl`	CorrectBench: Automatic Testbench Generation with Functional Self-Correction using LLMs for HDL Design. CoRR Ruidi Qiu, Grace Li Zhang, Rolf Drechsler, Ulf Schlichtmann, Bing Li
2024	J	`jnl`	CorrectNet+: Dealing With HW Non-Idealities in In-Memory-Computing Platforms by Error Suppression and Compensation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Amro Eldebiky, Grace Li Zhang, Georg Böcherer, Bing Li, Ulf Schlichtmann
2024	—	`conf`	Early-Exit with Class Exclusion for Efficient Inference of Neural Networks. AICAS Jingcun Wang, Bing Li, Grace Li Zhang
2024	J	`jnl`	EncodingNet: A Novel Encoding-Based MAC Design for Efficient Neural Network Acceleration. IEEE Trans. Circuits Syst. Artif. Intell. Bo Liu, Bing Li, Grace Li Zhang, Xunzhao Yin, Cheng Zhuo, Ulf Schlichtmann
2024	J	`jnl`	EncodingNet: A Novel Encoding-based MAC Design for Efficient Neural Network Acceleration. CoRR Bo Liu, Grace Li Zhang, Xunzhao Yin, Ulf Schlichtmann, Bing Li
2024	J	`jnl`	LLM-Aided Efficient Hardware Design Automation. CoRR Kangwei Xu, Ruidi Qiu, Zhuorui Zhao, Grace Li Zhang, Ulf Schlichtmann, Bing Li
2024	J	`jnl`	LiveMind: Low-latency Large Language Models with Simultaneous Inference. CoRR Chuangtao Chen, Grace Li Zhang, Xunzhao Yin, Cheng Zhuo, Ulf Schlichtmann, Bing Li
2024	B	`conf`	Logic Design of Neural Networks for High-Throughput and Low-Power Applications. ASPDAC Kangwei Xu, Grace Li Zhang, Ulf Schlichtmann, Bing Li
2024	A	`conf`	OplixNet: Towards Area-Efficient Optical Split-Complex Networks with Real-to-Complex Data Assignment and Knowledge Distillation. DATE Ruidi Qiu, Amro Eldebiky, Grace Li Zhang, Xunzhao Yin, Cheng Zhuo, Ulf Schlichtmann, Bing Li
2024	A	`conf`	ScanCamouflage: Obfuscating Scan Chains with Camouflaged Sequential and Logic Gates. DATE Tarik Ibrahimpasic, Grace Li Zhang, Michaela Brunner, Georg Sigl, Bing Li, Ulf Schlichtmann
2023	A	`conf`	A Novel and Efficient Block-Based Programming for ReRAM-Based Neuromorphic Computing. ICCAD Wei-Lun Chen, Fang-Yi Gu, Ing-Chao Lin, Grace Li Zhang, Bing Li, Ulf Schlichtmann
2023	—	`conf`	Area-Efficient Neural Network CD Equalizer for 4×200Gb/s PAM4 CWDM4 Systems. OFC Bo Liu, Christian Blümm, Stefano Calabrò, Bing Li, Ulf Schlichtmann
2023	J	`jnl`	BRoCoM: A Bayesian Framework for Robust Computing on Memristor Crossbar. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Di Gao, Zeyu Yang, Qingrong Huang, Grace Li Zhang, Xunzhao Yin, Bing Li, Ulf Schlichtmann, Cheng Zhuo
2023	A	`conf`	Class-based Quantization for Neural Networks. DATE Wenhao Sun, Grace Li Zhang, Huaxi Gu, Bing Li, Ulf Schlichtmann
2023	A	`conf`	CorrectNet: Robustness Enhancement of Analog In-Memory Computing for Neural Networks by Error Suppression and Compensation. DATE Amro Eldebiky, Grace Li Zhang, Georg Böcherer, Bing Li, Ulf Schlichtmann
2023	A	`conf`	Countering Uncertainties in In-Memory-Computing Platforms with Statistical Training, Accuracy Compensation and Recursive Test. DATE Amro Eldebiky, Grace Li Zhang, Bing Li
2023	J	`jnl`	Early Classification for Dynamic Inference of Neural Networks. CoRR Jingcun Wang, Bing Li, Grace Li Zhang
2023	J	`jnl`	Expressivity Enhancement with Efficient Quadratic Neurons for Convolutional Neural Networks. CoRR Chuangtao Chen, Grace Li Zhang, Xunzhao Yin, Cheng Zhuo, Ulf Schlichtmann, Bing Li
2023	J	`jnl`	Ferroelectric Ternary Content Addressable Memories for Energy-Efficient Associative Search. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Xunzhao Yin, Yu Qian, Mohsen Imani, Kai Ni, Chao Li, Grace Li Zhang, Bing Li, Ulf Schlichtmann, Cheng Zhuo
2023	J	`jnl`	Guest Editors' Introduction: Special Issue on Machine Learning for CAD/EDA. IEEE Des. Test Ulf Schlichtmann, Bing Li, Bei Yu, Raviv Gal
2023	—	`conf`	Implementation of a Robust and Power-Efficient Nonlinear 64-QAM Demapper using In-Memory Computing. OFC Amro Eldebiky, Georg Böcherer, Maximilian Schädler, Stefano Calabrò, Bing Li, Ulf Schlichtmann
2023	J	`jnl`	Logic Design of Neural Networks for High-Throughput and Low-Power Applications. CoRR Kangwei Xu, Grace Li Zhang, Ulf Schlichtmann, Bing Li
2023	J	`jnl`	Machine Learning in Advanced IC Design: A Methodological Survey. IEEE Des. Test Tinghuan Chen, Grace Li Zhang, Bei Yu, Bing Li, Ulf Schlichtmann
2023	A	`conf`	NearUni: Near-Unitary Training for Efficient Optical Neural Networks. ICCAD Amro Eldebiky, Bing Li, Grace Li Zhang
2023	J	`jnl`	OplixNet: Towards Area-Efficient Optical Split-Complex Networks with Real-to-Complex Data Assignment and Knowledge Distillation. CoRR Ruidi Qiu, Amro Eldebiky, Grace Li Zhang, Xunzhao Yin, Cheng Zhuo, Ulf Schlichtmann, Bing Li
2023	A*	`conf`	PowerPruning: Selecting Weights and Activations for Power-Efficient Neural Network Acceleration. DAC Richard Petri, Grace Li Zhang, Yiran Chen, Ulf Schlichtmann, Bing Li
2023	J	`jnl`	PowerPruning: Selecting Weights and Activations for Power-Efficient Neural Network Acceleration. CoRR Richard Petri, Grace Li Zhang, Yiran Chen, Ulf Schlichtmann, Bing Li
2023	A	`conf`	SteppingNet: A Stepping Neural Network with Incremental Accuracy Enhancement. DATE Wenhao Sun, Grace Li Zhang, Xunzhao Yin, Cheng Zhuo, Huaxi Gu, Bing Li, Ulf Schlichtmann
2022	A*	`conf`	ASTERS: adaptable threshold spike-timing neuromorphic design with twin-column ReRAM synapses. DAC Ziru Li, Qilin Zheng, Bonan Yan, Ru Huang, Bing Li, Yiran Chen
2022	C	`conf`	Aging Aware Retraining for Memristor-based Neuromorphic Computing. ISCAS Wenwen Ye, Grace Li Zhang, Bing Li, Ulf Schlichtmann, Cheng Zhuo, Xunzhao Yin
2022	J	`jnl`	Class-based Quantization for Neural Networks. CoRR Wenhao Sun, Grace Li Zhang, Huaxi Gu, Bing Li, Ulf Schlichtmann
2022	J	`jnl`	Computer-aided Design Techniques for Flow-based Microfluidic Lab-on-a-chip Systems. ACM Comput. Surv. Xing Huang, Tsung-Yi Ho, Wenzhong Guo, Bing Li, Krishnendu Chakrabarty, Ulf Schlichtmann
2022	J	`jnl`	Contamination-Aware Synthesis for Programmable Microfluidic Devices. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Hui-Chieh Yu, Yu-Huei Lin, Zhiyang Chen, Bing Li, Xing Huang, Ulf Schlichtmann, Tsung-Yi Ho, Hailong Yao
2022	J	`jnl`	CorrectNet: Robustness Enhancement of Analog In-Memory Computing for Neural Networks by Error Suppression and Compensation. CoRR Amro Eldebiky, Grace Li Zhang, Georg Böcherer, Bing Li, Ulf Schlichtmann
2022	A*	`conf`	Energy efficient data search design and optimization based on a compact ferroelectric FET content addressable memory. DAC Jiahao Cai, Mohsen Imani, Kai Ni, Grace Li Zhang, Bing Li, Ulf Schlichtmann, Cheng Zhuo, Xunzhao Yin
2022	J	`jnl`	Flow-Based Microfluidic Biochips With Distributed Channel Storage: Synthesis, Physical Design, and Wash Optimization. IEEE Trans. Computers Xing Huang, Wenzhong Guo, Zhisheng Chen, Bing Li, Tsung-Yi Ho, Ulf Schlichtmann
2022	J	`jnl`	MiniControl 2.0: Co-Synthesis of Flow and Control Layers for Microfluidic Biochips With Strictly Constrained Control Ports. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Xing Huang, Tsung-Yi Ho, Zepeng Li, Genggeng Liu, Lu Wang, Qingshan Li, Wenzhong Guo, Bing Li, Ulf Schlichtmann
2022	J	`jnl`	Mixer-Based Washing Methods for Programmable Microfluidic Devices. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yifang Bao, Shigeru Yamashita, Bing Li, Tsung-Yi Ho
2022	J	`jnl`	PathDriver+: Enhanced Path-Driven Architecture Design for Flow-Based Microfluidic Biochips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Xing Huang, Youlin Pan, Grace Li Zhang, Bing Li, Wenzhong Guo, Tsung-Yi Ho, Ulf Schlichtmann
2022	J	`jnl`	SteppingNet: A Stepping Neural Network with Incremental Accuracy Enhancement. CoRR Wenhao Sun, Grace Li Zhang, Xunzhao Yin, Cheng Zhuo, Huaxi Gu, Bing Li, Ulf Schlichtmann
2022	J	`jnl`	VirtualSync+: Timing Optimization With Virtual Synchronization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Grace Li Zhang, Bing Li, Xing Huang, Xunzhao Yin, Cheng Zhuo, Masanori Hashimoto, Ulf Schlichtmann
2022	J	`jnl`	VirtualSync+: Timing Optimization with Virtual Synchronization. CoRR Grace Li Zhang, Bing Li, Xing Huang, Xunzhao Yin, Cheng Zhuo, Masanori Hashimoto, Ulf Schlichtmann
2021	J	`jnl`	A Reconfigurable Multiplier for Signed Multiplications with Asymmetric Bit-Widths. ACM J. Emerg. Technol. Comput. Syst. Chuliang Guo, Li Zhang, Xian Zhou, Grace Li Zhang, Bing Li, Weikang Qian, Xunzhao Yin, Cheng Zhuo
2021	A	`conf`	An Efficient Programming Framework for Memristor-based Neuromorphic Computing. DATE Grace Li Zhang, Bing Li, Xing Huang, Chen Shen, Shuhang Zhang, Florin Burcea, Helmut Graeb, Tsung-Yi Ho, Hai Li, Ulf Schlichtmann
2021	A*	`conf`	Bayesian Inference Based Robust Computing on Memristor Crossbar. DAC Di Gao, Qingrong Huang, Grace Li Zhang, Xunzhao Yin, Bing Li, Ulf Schlichtmann, Cheng Zhuo
2021	J	`jnl`	DCSA: Distributed Channel-Storage Architecture for Flow-Based Microfluidic Biochips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chunfeng Liu, Xing Huang, Bing Li, Hailong Yao, Paul Pop, Tsung-Yi Ho, Ulf Schlichtmann
2021	A	`conf`	Energy-Aware Designs of Ferroelectric Ternary Content Addressable Memory. DATE Yu Qian, Zhenhao Fan, Haoran Wang, Chao Li, Mohsen Imani, Kai Ni, Grace Li Zhang, Bing Li, Ulf Schlichtmann, Cheng Zhuo, Xunzhao Yin
2021	A	`conf`	Hardware-Software Codesign of Weight Reshaping and Systolic Array Multiplexing for Efficient CNNs. DATE Jingyao Zhang, Huaxi Gu, Grace Li Zhang, Bing Li, Ulf Schlichtmann
2021	—	`conf`	Interference-Free Design Methodology for Paper-Based Digital Microfluidic Biochips. ASP-DAC Yun-Chen Lo, Bing Li, Sooyong Park, Kwanwoo Shin, Tsung-Yi Ho
2021	A	`conf`	Reliable Memristor-based Neuromorphic Design Using Variation- and Defect-Aware Training. ICCAD Di Gao, Grace Li Zhang, Xunzhao Yin, Bing Li, Ulf Schlichtmann, Cheng Zhuo
2021	—	`conf`	RobustONoC: Fault-Tolerant Optical Networks-on-Chip with Path Backup and Signal Reflection. ISQED Yu-Kai Chuang, Yong Zhong, Yi-Hao Cheng, Bo-Yi Yu, Shao-Yun Fang, Bing Li, Ulf Schlichtmann
2021	—	`conf`	Robustness of Neuromorphic Computing with RRAM-based Crossbars and Optical Neural Networks. ASP-DAC Grace Li Zhang, Bing Li, Ying Zhu, Tianchen Wang, Yiyu Shi, Xunzhao Yin, Cheng Zhuo, Huaxi Gu, Tsung-Yi Ho, Ulf Schlichtmann
2020	A	`conf`	A Pulse-width Modulation Neuron with Continuous Activation for Processing-In-Memory Engines. DATE Shuhang Zhang, Bing Li, Hai Helen Li, Ulf Schlichtmann
2020	A	`conf`	Countering Variations and Thermal Effects for Accurate Optical Neural Networks. ICCAD Ying Zhu, Grace Li Zhang, Bing Li, Xunzhao Yin, Cheng Zhuo, Huaxi Gu, Tsung-Yi Ho, Ulf Schlichtmann
2020	J	`jnl`	Integrated Control-Fluidic Codesign Methodology for Paper-Based Digital Microfluidic Biochips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Qin Wang, Ulf Schlichtmann, Yici Cai, Weiqing Ji, Zeyan Li, Haena Cheong, Oh-Sun Kwon, Hailong Yao, Tsung-Yi Ho, Kwanwoo Shin, Bing Li
2020	—	`conf`	Lifetime Enhancement for RRAM-based Computing-In-Memory Engine Considering Aging and Thermal Effects. AICAS Shuhang Zhang, Grace Li Zhang, Bing Li, Hai Helen Li, Ulf Schlichtmann
2020	J	`jnl`	Multicontrol: Advanced Control-Logic Synthesis for Flow-Based Microfluidic Biochips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ying Zhu, Xing Huang, Bing Li, Tsung-Yi Ho, Qin Wang, Hailong Yao, Robert Wille, Ulf Schlichtmann
2020	A	`conf`	PathDriver: A Path-Driven Architectural Synthesis Flow for Continuous-Flow Microfluidic Biochips. ICCAD Xing Huang, Youlin Pan, Grace Li Zhang, Bing Li, Wenzhong Guo, Tsung-Yi Ho, Ulf Schlichtmann
2020	—	`conf`	Reliable and Robust RRAM-based Neuromorphic Computing. ACM Great Lakes Symposium on VLSI Grace Li Zhang, Bing Li, Ying Zhu, Shuhang Zhang, Tianchen Wang, Yiyu Shi, Tsung-Yi Ho, Hai (Helen) Li, Ulf Schlichtmann
2020	A	`conf`	Statistical Training for Neuromorphic Computing using Memristor-based Crossbars Considering Process Variations and Noise. DATE Ying Zhu, Grace Li Zhang, Tianchen Wang, Bing Li, Yiyu Shi, Tsung-Yi Ho, Ulf Schlichtmann
2020	J	`jnl`	Test Generation for Flow-Based Microfluidic Biochips With General Architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chunfeng Liu, Bing Li, Bhargab B. Bhattacharya, Krishnendu Chakrabarty, Tsung-Yi Ho, Ulf Schlichtmann
2020	—	`conf`	Timing Resilience for Efficient and Secure Circuits. ASP-DAC Grace Li Zhang, Michaela Brunner, Bing Li, Georg Sigl, Ulf Schlichtmann
2020	J	`jnl`	TimingCamouflage+: Netlist Security Enhancement With Unconventional Timing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Grace Li Zhang, Bing Li, Meng Li, Bei Yu, David Z. Pan, Michaela Brunner, Georg Sigl, Ulf Schlichtmann
2020	J	`jnl`	TimingCamouflage+: Netlist Security Enhancement with Unconventional Timing (with Appendix). CoRR Grace Li Zhang, Bing Li, Meng Li, Bei Yu, David Z. Pan, Michaela Brunner, Georg Sigl, Ulf Schlichtmann
2020	A	`conf`	Transport-Free Module Binding for Sample Preparation using Microfluidic Fully Programmable Valve Arrays. DATE Gautam Choudhary, Sandeep Pal, Debraj Kundu, Sukanta Bhattacharjee, Shigeru Yamashita, Bing Li, Ulf Schlichtmann, Sudip Roy
2019	A	`conf`	Aging-aware Lifetime Enhancement for Memristor-based Neuromorphic Computing. DATE Shuhang Zhang, Grace Li Zhang, Bing Li, Hai Helen Li, Ulf Schlichtmann
2019	A	`conf`	Block-Flushing: A Block-based Washing Algorithm for Programmable Microfluidic Devices. DATE Yu-Huei Lin, Tsung-Yi Ho, Bing Li, Ulf Schlichtmann
2019	J	`jnl`	EffiTest2: Efficient Delay Test and Prediction for Post-Silicon Clock Skew Configuration Under Process Variations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Grace Li Zhang, Bing Li, Yiyu Shi, Jiang Hu, Ulf Schlichtmann
2019	A	`conf`	Fault Localization in Programmable Microfluidic Devices. DATE Alessandro Bernardini, Chunfeng Liu, Bing Li, Ulf Schlichtmann
2019	J	`jnl`	MEMS-IC Robustness Optimization Considering Electrical and Mechanical Design and Process Parameters. ACM Trans. Design Autom. Electr. Syst. Florin Burcea, Andreas Herrmann, Bing Li, Helmut Graeb
2019	A*	`conf`	MiniControl: Synthesis of Continuous-Flow Microfluidics with Strictly Constrained Control Ports. DAC Xing Huang, Tsung-Yi Ho, Wenzhong Guo, Bing Li, Ulf Schlichtmann
2019	A	`conf`	Physical Synthesis of Flow-Based Microfluidic Biochips Considering Distributed Channel Storage. DATE Zhisheng Chen, Xing Huang, Wenzhong Guo, Bing Li, Tsung-Yi Ho, Ulf Schlichtmann
2018	C	`conf`	Automatic Design of Microfluidic Devices. FDL Robert Wille, Bing Li, Rolf Drechsler, Ulf Schlichtmann
2018	J	`jnl`	Columba 2.0: A Co-Layout Synthesis Tool for Continuous-Flow Microfluidic Biochips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Tsun-Ming Tseng, Mengchu Li, Daniel Nestor Freitas, Travis McAuley, Bing Li, Tsung-Yi Ho, Ismail Emre Araci, Ulf Schlichtmann
2018	J	`jnl`	Design-Phase Buffer Allocation for Post-Silicon Clock Binning by Iterative Learning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Grace Li Zhang, Bing Li, Jinglan Liu, Yiyu Shi, Ulf Schlichtmann
2018	A*	`conf`	Design-for-testability for continuous-flow microfluidic biochips. DAC Chunfeng Liu, Bing Li, Tsung-Yi Ho, Krishnendu Chakrabarty, Ulf Schlichtmann
2018	J	`jnl`	Efficient spanning-tree-based test pattern generation for Programmable Microfluidic Devices. Microelectron. J. Alessandro Bernardini, Chunfeng Liu, Bing Li, Ulf Schlichtmann
2018	J	`jnl`	From Process Variations to Reliability: A Survey of Timing of Digital Circuits in the Nanometer Era. IPSJ Trans. Syst. LSI Des. Methodol. Bing Li, Masanori Hashimoto, Ulf Schlichtmann
2018	—	`conf`	MEMS-IC Optimization Considering Design Parameters and Manufacturing Variation from both Mechanical and Electrical Side. ICECS Florin Burcea, Andreas Herrmann, Bing Li, Helmut Graeb
2018	A	`conf`	Multi-channel and fault-tolerant control multiplexing for flow-based microfluidic biochips. ICCAD Ying Zhu, Bing Li, Tsung-Yi Ho, Qin Wang, Hailong Yao, Robert Wille, Ulf Schlichtmann
2018	A*	`conf`	PlanarONoC: concurrent placement and routing considering crossing minimization for optical networks-on-chip. DAC Yu-Kai Chuang, Kuan-Jung Chen, Kun-Lin Lin, Shao-Yun Fang, Bing Li, Ulf Schlichtmann
2018	—	`conf`	Test generation for microfluidic fully programmable valve arrays (FPVAs) with heuristic acceleration. ICICDT Chunfeng Liu, Bing Li, Bhargab B. Bhattacharya, Krishnendu Chakrabarty, Tsung-Yi Ho, Ulf Schlichtmann
2018	C	`conf`	Thermal-Aware Placement and Routing for 3D Optical Networks-on-Chips. ISCAS Fengxian Jiao, Sheqin Dong, Bei Yu, Bing Li, Ulf Schlichtmann
2018	—	`conf`	Timing with Virtual Signal Synchronization for Circuit Performance and Netlist Security. ISVLSI Grace Li Zhang, Bing Li, Ulf Schlichtmann
2018	A	`conf`	TimingCamouflage: Improving circuit security against counterfeiting by unconventional timing. DATE Grace Li Zhang, Bing Li, Bei Yu, David Z. Pan, Ulf Schlichtmann
2018	A*	`conf`	Virtualsync: timing optimization by synchronizing logic waves with sequential and combinational components as delay units. DAC Grace Li Zhang, Bing Li, Masanori Hashimoto, Ulf Schlichtmann
2017	J	`jnl`	An Efficient Two-Phase ILP-Based Algorithm for Precise CMOS RFIC Layout Generation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Tsun-Ming Tseng, Bing Li, Ching-Feng Yeh, Hsiang-Chieh Jhan, Zuo-Min Tsai, Mark Po-Hung Lin, Ulf Schlichtmann
2017	—	`conf`	Application of machine learning methods in post-silicon yield improvement. SoCC Baris Yigit, Grace Li Zhang, Bing Li, Yiyu Shi, Ulf Schlichtmann
2017	A*	`conf`	Component-Oriented High-level Synthesis for Continuous-Flow Microfluidics Considering Hybrid-Scheduling. DAC Mengchu Li, Tsun-Ming Tseng, Bing Li, Tsung-Yi Ho, Ulf Schlichtmann
2017	—	`conf`	Design automation for Labs-on-Chip: A new "playground" for SoC designers. SoCC Robert Wille, Bing Li
2017	J	`jnl`	Design-Phase Buffer Allocation for Post-Silicon Clock Binning by Iterative Learning. CoRR Grace Li Zhang, Bing Li, Jinglan Liu, Yiyu Shi, Ulf Schlichtmann
2017	J	`jnl`	EffiTest: Efficient Delay Test and Statistical Prediction for Configuring Post-silicon Tunable Buffers. CoRR Grace Li Zhang, Bing Li, Ulf Schlichtmann
2017	J	`jnl`	Fast Statistical Timing Analysis for Circuits with Post-Silicon Tunable Clock Buffers. CoRR Bing Li, Ning Chen, Ulf Schlichtmann
2017	—	`conf`	Hamming-distance-based valve-switching optimization for control-layer multiplexing in flow-based microfluidic biochips. ASP-DAC Qin Wang, Shiliang Zuo, Hailong Yao, Tsung-Yi Ho, Bing Li, Ulf Schlichtmann, Yici Cai
2017	J	`jnl`	ILP-based Alleviation of Dense Meander Segments with Prioritized Shifting and Progressive Fixing in PCB Routing. CoRR Tsun-Ming Tseng, Bing Li, Tsung-Yi Ho, Ulf Schlichtmann
2017	J	`jnl`	Novel CMOS RFIC Layout Generation with Concurrent Device Placement and Fixed-Length Microstrip Routing. CoRR Tsun-Ming Tseng, Bing Li, Ching-Feng Yeh, Hsiang-Chieh Jhan, Zuo-Min Tsai, Mark Po-Hung Lin, Ulf Schlichtmann
2017	J	`jnl`	On Hierarchical Statistical Static Timing Analysis. CoRR Bing Li, Ning Chen, Manuel Schmidt, Walter Schneider, Ulf Schlichtmann
2017	J	`jnl`	On Timing Model Extraction and Hierarchical Statistical Timing Analysis. CoRR Bing Li, Ning Chen, Yang Xu, Ulf Schlichtmann
2017	J	`jnl`	PieceTimer: A Holistic Timing Analysis Framework Considering Setup/Hold Time Interdependency Using A Piecewise Model. CoRR Grace Li Zhang, Bing Li, Ulf Schlichtmann
2017	J	`jnl`	Post-Route Alleviation of Dense Meander Segments in High-Performance Printed Circuit Boards. CoRR Tsun-Ming Tseng, Bing Li, Tsung-Yi Ho, Ulf Schlichtmann
2017	J	`jnl`	Post-Route Refinement for High-Frequency PCBs Considering Meander Segment Alleviation. CoRR Tsun-Ming Tseng, Bing Li, Tsung-Yi Ho, Ulf Schlichtmann
2017	J	`jnl`	Pressure-Aware Control Layer Optimization for Flow-Based Microfluidic Biochips. IEEE Trans. Biomed. Circuits Syst. Qin Wang, Yue Xu, Shiliang Zuo, Hailong Yao, Tsung-Yi Ho, Bing Li, Ulf Schlichtmann, Yici Cai
2017	—	`conf`	Reliability-aware synthesis and fault test of fully programmable valve arrays (FPVAs). DFT Bing Li, Ulf Schlichtmann
2017	J	`jnl`	Sampling-based Buffer Insertion for Post-Silicon Yield Improvement under Process Variability. CoRR Grace Li Zhang, Bing Li, Ulf Schlichtmann
2017	J	`jnl`	Static Timing Model Extraction for Combinational Circuits. CoRR Bing Li, Christoph Knoth, Walter Schneider, Manuel Schmidt, Ulf Schlichtmann
2017	J	`jnl`	Statistical Timing Analysis and Criticality Computation for Circuits with Post-Silicon Clock Tuning Elements. CoRR Bing Li, Ulf Schlichtmann
2017	J	`jnl`	Statistical Timing Analysis for Latch-Controlled Circuits with Reduced Iterations and Graph Transformations. CoRR Bing Li, Ning Chen, Ulf Schlichtmann
2017	J	`jnl`	Storage and Caching: Synthesis of Flow-based Microfluidic Biochips. CoRR Tsun-Ming Tseng, Bing Li, Tsung-Yi Ho, Ulf Schlichtmann
2017	J	`jnl`	Testing Microfluidic Fully Programmable Valve Arrays (FPVAs). CoRR Chunfeng Liu, Bing Li, Bhargab B. Bhattacharya, Krishnendu Chakrabarty, Tsung-Yi Ho, Ulf Schlichtmann
2017	A	`conf`	Testing microfluidic Fully Programmable Valve Arrays (FPVAs). DATE Chunfeng Liu, Bing Li, Bhargab B. Bhattacharya, Krishnendu Chakrabarty, Tsung-Yi Ho, Ulf Schlichtmann
2017	J	`jnl`	Timing Model Extraction for Sequential Circuits Considering Process Variations. CoRR Bing Li, Ning Chen, Ulf Schlichtmann
2017	J	`jnl`	Transport or Store? Synthesizing Flow-based Microfluidic Biochips using Distributed Channel Storage. CoRR Chunfeng Liu, Bing Li, Hailong Yao, Paul Pop, Tsung-Yi Ho, Ulf Schlichtmann
2017	A*	`conf`	Transport or Store?: Synthesizing Flow-based Microfluidic Biochips using Distributed Channel Storage. DAC Chunfeng Liu, Bing Li, Hailong Yao, Paul Pop, Tsung-Yi Ho, Ulf Schlichtmann
2017	—	`conf`	W3B: Special session: Secure multi-processors systems-on-chip for critical applications. SoCC Bing Li
2016	A*	`conf`	Columba: co-layout synthesis for continuous-flow microfluidic biochips. DAC Tsun-Ming Tseng, Mengchu Li, Bing Li, Tsung-Yi Ho, Ulf Schlichtmann
2016	A	`conf`	Control-fluidic CoDesign for paper-based digital microfluidic biochips. ICCAD Qin Wang, Zeyan Li, Haena Cheong, Oh-Sun Kwon, Hailong Yao, Tsung-Yi Ho, Kwanwoo Shin, Bing Li, Ulf Schlichtmann, Yici Cai
2016	A*	`conf`	EffiTest: efficient delay test and statistical prediction for configuring post-silicon tunable buffers. DAC Grace Li Zhang, Bing Li, Ulf Schlichtmann
2016	A	`conf`	From biochips to quantum circuits: computer-aided design for emerging technologies. ICCAD Robert Wille, Bing Li, Ulf Schlichtmann, Rolf Drechsler
2016	A*	`conf`	Novel CMOS RFIC layout generation with concurrent device placement and fixed-length microstrip routing. DAC Tsun-Ming Tseng, Bing Li, Ching-Feng Yeh, Hsiang-Chieh Jhan, Zuo-Min Tsai, Mark Po-Hung Lin, Ulf Schlichtmann
2016	A	`conf`	PieceTimer: a holistic timing analysis framework considering setup/hold time interdependency using a piecewise model. ICCAD Grace Li Zhang, Bing Li, Ulf Schlichtmann
2016	—	`conf`	Reliability, adaptability and flexibility in timing: Buy a life insurance for your circuits. ASP-DAC Ulf Schlichtmann, Masanori Hashimoto, Iris Hui-Ru Jiang, Bing Li
2016	J	`jnl`	Reliability-Aware Synthesis With Dynamic Device Mapping and Fluid Routing for Flow-Based Microfluidic Biochips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Tsun-Ming Tseng, Bing Li, Mengchu Li, Tsung-Yi Ho, Ulf Schlichtmann
2016	A	`conf`	Sampling-based buffer insertion for post-silicon yield improvement under process variability. DATE Grace Li Zhang, Bing Li, Ulf Schlichtmann
2016	A	`conf`	Sieve-valve-aware synthesis of flow-based microfluidic biochips considering specific biological execution limitations. DATE Mengchu Li, Tsun-Ming Tseng, Bing Li, Tsung-Yi Ho, Ulf Schlichtmann
2015	J	`jnl`	ILP-Based Alleviation of Dense Meander Segments With Prioritized Shifting and Progressive Fixing in PCB Routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Tsun-Ming Tseng, Bing Li, Tsung-Yi Ho, Ulf Schlichtmann
2015	A*	`conf`	Reliability-aware synthesis for flow-based microfluidic biochips by dynamic-device mapping. DAC Tsun-Ming Tseng, Bing Li, Tsung-Yi Ho, Ulf Schlichtmann
2015	J	`jnl`	Statistical Timing Analysis and Criticality Computation for Circuits With Post-Silicon Clock Tuning Elements. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Bing Li, Ulf Schlichtmann
2015	J	`jnl`	Storage and Caching: Synthesis of Flow-Based Microfluidic Biochips. IEEE Des. Test Tsun-Ming Tseng, Bing Li, Ulf Schlichtmann, Tsung-Yi Ho
2015	A	`conf`	Timing verification for adaptive integrated circuits. DATE Rohit Kumar, Bing Li, Yiren Shen, Ulf Schlichtmann, Jiang Hu
2013	J	`jnl`	On Timing Model Extraction and Hierarchical Statistical Timing Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Bing Li, Ning Chen, Yang Xu, Ulf Schlichtmann
2013	A	`conf`	Post-route alleviation of dense meander segments in high-performance printed circuit boards. ICCAD Tsun-Ming Tseng, Bing Li, Tsung-Yi Ho, Ulf Schlichtmann
2013	—	`conf`	Post-route refinement for high-frequency PCBs considering meander segment alleviation. ACM Great Lakes Symposium on VLSI Tsun-Ming Tseng, Bing Li, Tsung-Yi Ho, Ulf Schlichtmann
2012	J	`jnl`	Iterative timing analysis based on nonlinear and interdependent flipflop modelling. IET Circuits Devices Syst. Ning Chen, Bing Li, Ulf Schlichtmann
2012	J	`jnl`	Statistical Timing Analysis for Latch-Controlled Circuits With Reduced Iterations and Graph Transformations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Bing Li, Ning Chen, Ulf Schlichtmann
2012	A	`conf`	Variation-aware leakage power model extraction for system-level hierarchical power analysis. DATE Yang Xu, Bing Li, Ralph Hasholzner, Bernhard Rohfleisch, Christian Haubelt, Jürgen Teich
2011	A	`conf`	Fast statistical timing analysis for circuits with Post-Silicon Tunable clock buffers. ICCAD Bing Li, Ning Chen
2011	—	`conf`	Iterative Timing Analysis Considering Interdependency of Setup and Hold Times. PATMOS Ning Chen, Bing Li, Ulf Schlichtmann
2011	—	`conf`	Timing Modeling of Flipflops Considering Aging Effects. PATMOS Ning Chen, Bing Li, Ulf Schlichtmann
2010	A	`conf`	Fast statistical timing analysis of latch-controlled circuits for arbitrary clock periods. ICCAD Bing Li, Ning Chen, Ulf Schlichtmann
2009	A	`conf`	On hierarchical statistical static timing analysis. DATE Bing Li, Ning Chen, Manuel Schmidt, Walter Schneider, Ulf Schlichtmann
2009	—	`conf`	Sensitivity based parameter reduction for statistical analysis of circuit performance. ICECS Ning Chen, Bing Li, Ulf Schlichtmann
2009	A	`conf`	Timing model extraction for sequential circuits considering process variations. ICCAD Bing Li, Ning Chen, Ulf Schlichtmann
2008	—	`conf`	A New Bounding Technique for Handling Arbitrary Correlations in Path-Based SSTA. PATMOS Walter Schneider, Manuel Schmidt, Bing Li, Ulf Schlichtmann
2008	—	`conf`	Static Timing Model Extraction for Combinational Circuits. PATMOS Bing Li, Christoph Knoth, Walter Schneider, Manuel Schmidt, Ulf Schlichtmann