Bing J. Sheu

73 papers A* 1B 3C 19Misc 4Journal 38Unranked 8
YearRankTypeTitle / Venue / Authors
2021 J jnl
Adaptive Floor Cleaning Strategy by Human Density Surveillance Mapping with a Reconfigurable Multi-Purpose Service Robot.
Sensors
Vinu Sivanantham, Anh Vu Le, Yuyao Shi, Mohan Rajesh Elara, Bing J. Sheu
2021 J jnl
Reinforcement Learning-Based Complete Area Coverage Path Planning for a Modified hTrihex Robot.
Sensors
Koppaka Ganesh Sai Apuroop, Anh Vu Le, Mohan Rajesh Elara, Bing J. Sheu
2015 — conf
Circuits evening panel discussion 1: Is university circuit design research and education keeping up with industry needs?
VLSIC
P. Yue, Bing J. Sheu, A. Matsuzawa, K. Asada, L. Loh, Kofi A. A. Makinwa, Shekhar Borkar, Vladimir Stojanovic
2002 — conf
An efficient parameter extraction method using statistical optimization in S-CMOS deep-submicron/nanometer model.
ISCAS (5)
Alex Yoondong Park, Steve H. Jen, Bing J. Sheu, Heesook Yoon, In Gyeom Kim
2001 J jnl
Brain-implantable biomimetic electronics as the next era in neural prosthetics.
Proc. IEEE
Theodore W. Berger, Michel Baudry, Roberta Diaz Brinton, Jim-Shih Liaw, Vasilis Z. Marmarelis, Alex Yoondong Park, Bing J. Sheu, Armand R. Tanguay
2001 A* conf
Panel: Is Nanometer Design Under Control?
DAC
Andrew B. Kahng, Bing J. Sheu, Nancy Nettleton, John M. Cohn, Shekhar Borkar, Louis Scheffer, Ed Cheng, Sang Wang
2000 — conf
Compact VLSI Neural Network Circuit with High-Capacity Dynamic Synapses.
IJCNN (4)
Alex Yoondong Park, Jim-Shih Liaw, Theodore W. Berger, Bing J. Sheu
1999 J jnl
A unified submicrometer MOS transistor charge/capacitance model for mixed-signal IC's.
IEEE J. Solid State Circuits
Steve H. Jen, Bing J. Sheu, Yoondong Park
1998 J jnl
A compact and unified MOS DC current model with highly continuous conductances for low-voltage ICs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Steve H. Jen, Bing J. Sheu
1997 J jnl
A CDMA communication detector with robust near-far resistance using paralleled array processors.
IEEE Trans. Circuits Syst. Video Technol.
David Cheng-Hsiung Chen, Bing J. Sheu, Wayne C. Young
1997 C conf
A Low Power Smart Vision System Based on Active Pixel Sensor Integrated with Programmable Neural Processor.
ICCD
Wai-Chi Fang, Guang Yang, Bedabrata Pain, Bing J. Sheu
1997 J jnl
Advances in efficient optical links to enhance desktop multimedia processor systems.
IEEE Trans. Circuits Syst. Video Technol.
Richard H. Tsai, Bing J. Sheu, Andrew Kostrzewski, Jeongdal Kim
1997 J jnl
Guest Editorial.
IEEE Trans. Circuits Syst. Video Technol.
Bing J. Sheu, Mohammed Ghanbari, Horng-Dar Lin, Chung-Yu Wu
1996 C conf
A Compact Neural Network Based CDMA Receiver for Multimedia Wireless Communication.
ICCD
David C. Chen, Bing J. Sheu, Theodore W. Berger
1996 — conf
A neural network communication equalizer with optimized solution capability.
ICNN
David C. Chen, Bing J. Sheu, Eric Y. Chou
1996 J jnl
Optimal solutions for cellular neural networks by paralleled hardware annealing.
IEEE Trans. Neural Networks
Sa Hyun Bang, Bing J. Sheu, Tony H. Wu
1996 — conf
VLSI design for real-time signal processing based on biologically realistic neural models.
ICNN
Richard H. Tsai, Bing J. Sheu, Theodore W. Berger
1995 — conf
A compact VLSI design for recursive neural networks with hardware annealing capability.
ICNN
Eric Y. Chou, Bing J. Sheu, Steve H. Jen
1995 — conf
A hippocampal model implementation using VLSI table-look-up and model-based approaches.
ICNN
Richard H. Tsai, Eric Y. Chou, Bing J. Sheu, Theodore W. Berger
1995 C conf
Constructing Intelligent Microsystems with Modular VLSI Networks Design.
ISCAS
Bing J. Sheu
1995 C conf
Smart-pixel array processors based on optimal cellular neural networks for space sensor applications.
ICCD
Wai-Chi Fang, Bing J. Sheu, Holger Venus, Rainer Sandau
1995 C conf
VLSI Design of Cellular Neutral Networks with Annealing and Optical Input Capabilities.
ISCAS
Bing J. Sheu, Sa Hyun Bang, Wai-Chi Fang
1995 C conf
VLSI Neural Network Implementation of a Hippocampal Model.
ISCAS
Bing J. Sheu, Theodore W. Berger, Tony H. Wu, Richard H. Tsai
1995 C conf
VLSI design of densely-connected array processors.
ICCD
Eric Y. Chou, Bing J. Sheu, Tony H. Wu, Robert C. Chang
1995 C conf
VLSI-Compatible Cellular Neural Networks with Optimal Solution Capability for Optimization.
ISCAS
Bing J. Sheu, Robert C. Chang, Tony H. Wu, Sa Hyun Bang
1994 C conf
A Gaussian Synapse Circuit for Analog VLSI Neural Networks.
ISCAS
Joongho Choi, Bing J. Sheu, Josephine C.-F. Chang
1994 J jnl
A Gaussian synapse circuit for analog VLSI neural networks.
IEEE Trans. Very Large Scale Integr. Syst.
Joongho Choi, Bing J. Sheu, Josephine C.-F. Chang
1994 J jnl
A monolithic GaAs receiver for optical interconnect systems.
IEEE J. Solid State Circuits
Joongho Choi, Bing J. Sheu, Oscal T.-C. Chen
1994 C conf
An Analog MOS Model for Circuit Simulation and Benchmark Test Results.
ISCAS
Robert Chen-Hao Chang, Bing J. Sheu
1994 J jnl
An adaptive vector quantizer based on the Gold-Washing method for image compression.
IEEE Trans. Circuits Syst. Video Technol.
Oscal T.-C. Chen, Bing J. Sheu, Zhen Zhang
1994 J jnl
BSIM plus: an advanced SPICE model for submicron MOS VLSI circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Sudhir M. Gowda, Bing J. Sheu
1994 J jnl
Image compression using self-organization networks.
IEEE Trans. Circuits Syst. Video Technol.
Oscal T.-C. Chen, Bing J. Sheu, Wai-Chi Fang
1994 C conf
Search of Optimal Solutions in Multi-Level Neural Networks.
ISCAS
Sa Hyun Bang, Bing J. Sheu, Josephine C.-F. Chang
1994 J jnl
Testing of programmable analog neural network chips.
J. VLSI Signal Process.
Sudhir M. Gowda, Bing J. Sheu, Wen-Jay Hsu
1994 J jnl
VLSI systolic binary tree-searched vector quantizer for image compression.
IEEE Trans. Very Large Scale Integr. Syst.
Wai-Chi Fang, Chi-Yung Chang, Bing J. Sheu, Oscal T.-C. Chen, John C. Curlander
1993 J jnl
A VLSI neuroprocessor for image restoration using analog computing-based systolic architecture.
J. VLSI Signal Process.
Ji-Chien Lee, Bing J. Sheu, Rama Chellappa
1993 J jnl
A high-precision VLSI winner-take-all circuit for self-organizing neural networks.
IEEE J. Solid State Circuits
Joongho Choi, Bing J. Sheu
1993 J jnl
A mixed-signal VLSI competitive neuroprocessor for video motion detection.
J. VLSI Signal Process.
Ji-Chien Lee, Bing J. Sheu, Rama Chellappa
1993 J jnl
A programmable analog VLSI neural network processor for communication receivers.
IEEE Trans. Neural Networks
Joongho Choi, Sa Hyun Bang, Bing J. Sheu
1993 J jnl
Design and characterization of analog VLSI neural network modules.
IEEE J. Solid State Circuits
Sudhir M. Gowda, Bing J. Sheu, Joongho Choi, Chang-Gyu Hwang, James S. Cable
1993 J jnl
Paralleled hardware annealing for optimal solutions on electronic neural networks.
IEEE Trans. Neural Networks
Bang W. Lee, Bing J. Sheu
1993 J jnl
VLSI neuroprocessors for video motion detection.
IEEE Trans. Neural Networks
Ji-Chien Lee, Bing J. Sheu, Wai-Chi Fang, Rama Chellappa
1992 J jnl
A VLSI neural processor for image data compression using self-organization networks.
IEEE Trans. Neural Networks
Wai-Chi Fang, Bing J. Sheu, Oscal T.-C. Chen, Joongho Choi
1992 J jnl
A mixed-signal VLSI neuroprocessor for image restoration.
IEEE Trans. Circuits Syst. Video Technol.
Ji-Chien Lee, Bing J. Sheu, Joongho Choi, Ramalingam Chellappa
1992 Misc conf
Adaptive vector quantizer for image compression using self-organization approach.
ICASSP
Oscal T.-C. Chen, Bing J. Sheu, Wai-Chi Fang
1992 J jnl
Advanced integrated-circuit reliability simulation including dynamic stress effects.
IEEE J. Solid State Circuits
Wen-Jay Hsu, Bing J. Sheu, Sudhir M. Gowda, Chang-Gyu Hwang
1992 B conf
An Adaptive High-Speed Lossy Data Compression.
Data Compression Conference
Oscal T.-C. Chen, Zhen Zhang, Bing J. Sheu
1992 Misc conf
Design of a multiprocessor DSP chip for flexible information processing.
ICASSP
Chia-Fen Chang, Bing J. Sheu, Hiroto Okada
1992 J jnl
General-purpose neural chips with electrically programmable synapses and gain-adjustable neurons.
IEEE J. Solid State Circuits
Bang W. Lee, Bing J. Sheu
1992 J jnl
Image Compression on a VLSI Neural-Based Vector Quantizer.
Inf. Process. Manag.
Oscal T.-C. Chen, Bing J. Sheu, Wai-Chi Fang
1991 C conf
A GaAs Receiver Module for Optoelectronic Computing and Interconnection.
ICCD
Joongho Choi, Bing J. Sheu
1991 B conf
A Neural Network Based VLSI Vector Quantizer for Real-Time Image Compression.
Data Compression Conference
Wai-Chi Fang, Bing J. Sheu, Oscal T.-C. Chen
1991 Misc conf
A VLSI neuroprocessor for real-time image flow computing.
ICASSP
Wai-Chi Fang, Bing J. Sheu, Ji-Chien Lee
1991 J jnl
Design of reliable VLSI circuits using simulation techniques.
IEEE J. Solid State Circuits
Wen-Jay Hsu, Bing J. Sheu, Sudhir M. Gowda
1991 J jnl
Modified Hopfield neural networks for retrieving the optimal solution.
IEEE Trans. Neural Networks
Bang W. Lee, Bing J. Sheu
1991 Misc conf
Real-time high-ratio image compression using adaptive VLSI neuroprocessors.
ICASSP
Bing J. Sheu, Wai-Chi Fang
1991 C conf
Testing of Analog Neural Array-Processor Chips.
ICCD
Wen-Jay Hsu, Bing J. Sheu, Sudhir M. Gowda
1990 J jnl
A high slew-rate CMOS amplifier for analog signal processing.
IEEE J. Solid State Circuits
Bang W. Lee, Bing J. Sheu
1990 C conf
Automatic layout generation for mixed analog-digital VLSI neural chips.
ICCD
David J. Chen, Bing J. Sheu
1990 C conf
Parallel digital image restoration using adaptive VLSI neural chips.
ICCD
Ji-Chien Lee, Bing J. Sheu
1990 C conf
Real-time computing of optical flow using adaptive VLSI neuroprocessors.
ICCD
Wai-Chi Fang, Bing J. Sheu, Ji-Chien Lee
1990 B conf
VLSI image processor using analog programmable synapses and neurons.
IJCNN
Bang W. Lee, Ji-Chien Lee, Bing J. Sheu
1989 J jnl
An integrated-circuit reliability simulator-RELY.
IEEE J. Solid State Circuits
Bing J. Sheu, Wen-Jay Hsu, Bang W. Lee
1989 J jnl
Design of a neural-based A/D converter using modified Hopfield network.
IEEE J. Solid State Circuits
Bang W. Lee, Bing J. Sheu
1989 C conf
Digital and analog integrated-circuit design with built-in reliability.
ICCD
Wen-Jay Hsu, Bing J. Sheu, Vance C. Tyree
1989 C conf
SLAM: a smart analog module layout generator for mixed analog-digital VLSI design.
ICCD
David J. Chen, Ji-Chien Lee, Bing J. Sheu
1989 J jnl
Temperature dependence modeling for MOS VLSI circuit simulation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chung-Ping Wan, Bing J. Sheu
1988 J jnl
An MOS transistor charge model for VLSI design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Bing J. Sheu, Wen-Jay Hsu, P. K. Ko
1988 — conf
An investigation on local minima of a Hopfield network for optimization circuits.
ICNN
Bang W. Lee, Bing J. Sheu
1988 J jnl
Characterization of GaAs MESFET gate capacitances.
IEEE J. Solid State Circuits
Chih-Ching Shih, Bing J. Sheu, Huy M. Le
1988 J jnl
Device and circuit simulation interface for an integrated VLSI design environment.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chung-Ping Wan, Bing J. Sheu, Shih-Lien Lu
1988 C conf
Knowledge-based analog circuit synthesis with flexible architecture.
ICCD
Antony H. Fung, David J. Chen, Ying-Nan Lai, Bing J. Sheu
1987 J jnl
Inverse-Geometry Dependence of MOS Transistor Electrical Parameters.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
M. C. Hsu, Bing J. Sheu