Bing-Chen Wu

13 papers B 1C 1Journal 10Unranked 1
YearRankTypeTitle / Venue / Authors
2025 B conf
SOP
AVSS
Ching-Hung Cheng, Hsiu-Fu Wu, Bing-Chen Wu, Khanh-Phong Bui, Van-Tin Luu, Ching-Chun Huang
2025 J jnl
SOP^2: Transfer Learning with Scene-Oriented Prompt Pool on 3D Object Detection.
CoRR
Ching-Hung Cheng, Hsiu-Fu Wu, Bing-Chen Wu, Khanh-Phong Bui, Van-Tin Luu, Ching-Chun Huang
2023 J jnl
An Error-Resilient RISC-V Microprocessor With a Fully Integrated DC-DC Voltage Regulator for Near-Threshold Operation in 28-nm CMOS.
IEEE J. Solid State Circuits
Bing-Chen Wu, Wei-Ting Chen, Tsung-Te Liu
2022 J jnl
A Lightweight Power Side-Channel Attack Protection Technique With Minimized Overheads Using On-Demand Current Equalizer.
IEEE Trans. Circuits Syst. II Express Briefs
Shih-Hao Cheng, Meng-Hsueh Lee, Bing-Chen Wu, Tsung-Te Liu
2021 — conf
A Fully Integrated Switched-Capacitor Voltage Regulator with Multi-Rate Successive Approximation Achieving 190 ps Transient FoM and 83.7% Conversion Efficiency.
VLSI Circuits
Bing-Chen Wu, Tsung-Te Liu
2020 J jnl
A 270-mV 6T SRAM Using Row-Based Dual-Phase V
IEEE Trans. Circuits Syst.
Chen-Hsuan Lu, Ying-Tuan Hsu, Bing-Chen Wu, Tsung-Te Liu
2019 J jnl
A Ripple Reduction Method for Switched-Capacitor DC-DC Voltage Converter Using Fully Digital Resistance Modulation.
IEEE Trans. Circuits Syst. I Regul. Pap.
Fu-Yan Xie, Bing-Chen Wu, Tsung-Te Liu
2019 J jnl
An Ultra-Low-Power Dual-Mode Automatic Sleep Staging Processor Using Neural-Network-Based Decision Tree.
IEEE Trans. Circuits Syst. I Regul. Pap.
Shang-Yuan Chang, Bing-Chen Wu, Yi-Long Liou, Rui-Xuan Zheng, Pei-Lin Lee, Tzi-Dar Chiueh, Tsung-Te Liu
2019 C conf
Variation-Resilient Design Techniques for Energy-Constrained Systems.
IOLTS
Bing-Chen Wu, Tsung-Te Liu
2018 J jnl
Circuit Sensing Techniques in Magnetoresistive Random-Access Memory.
J. Low Power Electron.
Bing-Chen Wu, Tsung-Te Liu
2018 J jnl
Parallel Balanced-Bit-Serial Design Technique for Ultra-Low-Voltage Circuits With Energy Saving and Area Efficiency Enhancement.
IEEE Trans. Circuits Syst. I Regul. Pap.
Bing-Chen Wu, I-Chyn Wey
2015 J jnl
Robust C-element design for soft-error mitigation.
IEICE Electron. Express
I-Chyn Wey, Bing-Chen Wu, Chien-Chang Peng, Cihun-Siyong Alex Gong, Changhong Yu
2014 J jnl
A low power-delay-product and robust Isolated-DICE based SEU-tolerant latch circuit design.
Microelectron. J.
I-Chyn Wey, Yu-Sheng Yang, Bing-Chen Wu, Chien-Chang Peng