Biju K. Raveendran

22 papers A 2C 4Misc 4Journal 9Unranked 3

Year	Rank	Type	Title / Venue / Authors
2024	J	`jnl`	CAMP: a hierarchical cache architecture for multi-core mixed criticality processors. Int. J. Parallel Emergent Distributed Syst. Arun S. Nair, Geeta Patil, Archit Agarwal, Aboli Vijayan Pai, Biju K. Raveendran, Sasikumar Punnekkat
2023	J	`jnl`	SACRED: Software Approach for Collaboration and Research Dissemination. Int. J. e Collab. Louella Colaco, Arun S. Nair, Anurag Madnawat, Biju K. Raveendran
2023	J	`jnl`	Task models for mixed criticality systems - a review. Int. J. Crit. Comput. Based Syst. Louella Colaco, Arun S. Nair, Biju K. Raveendran, Sasikumar Punnekkat
2023	J	`jnl`	mcDVFS: cycle conserving DVFS scheduler for multi-core mixed criticality systems. Int. J. Parallel Emergent Distributed Syst. Louella Colaco, Prashiksha Jain, Arun S. Nair, Biju K. Raveendran, Sasikumar Punnekkat
2021	C	`conf`	MOESIL: A Cache Coherency Protocol for Locked Mixed Criticality L1 Data Cache. DS-RT Arun S. Nair, Aboli Vijayan Pai, Biju K. Raveendran, Geeta Patil
2021	—	`conf`	pmcEDF: An Energy Efficient Procrastination Scheduler for Multi-core Mixed Criticality Systems. HPCC/DSS/SmartCity/DependSys Louella Colaco, Amol Pai, Biju K. Raveendran, Sasikumar Punnekkat
2019	J	`jnl`	DPVFS: a dynamic procrastination cum DVFS scheduler for multi-core hard real-time systems. Int. J. Embed. Syst. Shubhangi K. Gawali, Biju K. Raveendran
2019	C	`conf`	MEDIATOR - A Mixed Criticality Deadline Honored Arbiter for Multi-core Real-time Systems. DS-RT Arun S. Nair, Louella Mesquita Colaco, Geeta Patil, Biju K. Raveendran, Sasikumar Punnekkat
2019	J	`jnl`	MOESIF: a MC/MP cache coherence protocol with improved bandwidth utilisation. Int. J. Embed. Syst. Geeta Patil, Neethu Bal Mallya, Biju K. Raveendran
2018	C	`conf`	SMILEY: A Mixed-Criticality Real-Time Task Scheduler for Multicore Systems. DS-RT Alen Sabu, Biju K. Raveendran, Rituparna Ghosh
2017	Misc	`conf`	DTLB: Deterministic TLB for Tightly Bound Hard Real-Time Systems. VLSID Kajal Varma, Geeta Patil, Biju K. Raveendran
2017	J	`jnl`	Energy efficient real-time scheduling algorithm for mixed task set on multi-core processors. Int. J. Embed. Syst. Mayuri Digalwar, Praveen Gahukar, Biju K. Raveendran, Sudeept Mohan
2017	J	`jnl`	LAMCS: A leakage aware DVFS based mixed task set scheduler for multi-core processors. Sustain. Comput. Informatics Syst. Mayuri Digalwar, Biju K. Raveendran, Sudeept Mohan
2017	J	`jnl`	eduCloud: a VM communication aware, migration efficient cloud for scientific computing. Int. J. Commun. Networks Distributed Syst. Biju K. Raveendran, Pravin Joshi, Sahil Mittal
2016	C	`conf`	DPS: A dynamic procrastination scheduler for multi-core/multi-processor hard real time systems. CoDIT Shubhangi K. Gawali, Biju K. Raveendran
2015	—	`conf`	Simulation based Performance Study of Cache Coherence Protocols. iNIS Neethu Bal Mallya, Geeta Patil, Biju K. Raveendran
2015	Misc	`conf`	Way Halted Prediction Cache: An Energy Efficient Cache Architecture for Embedded Processors. VLSID Neethu Bal Mallya, Geeta Patil, Biju K. Raveendran
2008	Misc	`conf`	Evaluation of priority based real time scheduling algorithms: choices and tradeoffs. SAC Biju K. Raveendran, Sundar Balasubramaniam, S. Gurunarayanan
2007	A	`conf`	An Energy Efficient Selective Placement Scheme for Set-Associative Data Cache in Embedded System. ESA Biju K. Raveendran, T. S. B. Sudarshan, Avinash Patil, Komal B. Randive, S. Gurunarayanan
2007	A	`conf`	EFFS: Efficient Flash File System for Wireless Sensor Nodes. ESA Biju K. Raveendran, Janardan Prasad Misra, Karan Bhatnagar, S. Gurunarayanan
2006	—	`conf`	A Context-Switch Reduction Heuristic for Power-Aware Off-Line Scheduling. Asia-Pacific Computer Systems Architecture Conference Biju K. Raveendran, Sundar Balasubramaniam, K. Durga Prasad, S. Gurunarayanan
2006	Misc	`conf`	Variants of Priority Scheduling Algorithms for Reducing Context-Switches in Real-Time Systems. ICDCN Biju K. Raveendran, K. Durga Prasad, Sundar Balasubramaniam, S. Gurunarayanan