Bijan Alizadeh

99 papers A* 1A 5B 4C 4Misc 4Journal 52Unranked 29

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	Real-time visual feature matching on FPGA platforms through adaptive local-patches processing. Multim. Tools Appl. Mohammad Dehnavi, Ehsan Pourshakib, Milad Sarhadi, Bijan Alizadeh
2025	J	`jnl`	AILIS: effective hardware accelerator for incremental learning with intelligent selection in classification. J. Supercomput. Nafiseh HosseinpourFardi, Bijan Alizadeh
2025	J	`jnl`	FPGA-based CNN accelerator using Convolutional Processing Element to reduce idle states. J. Syst. Archit. Mohammad Dehnavi, Aran Ghasemi, Bijan Alizadeh
2025	J	`jnl`	FixRTL: Auto-correction of Multiple RTL Bugs by a New Feature Burst Clustering Algorithm and Mutation. ACM Trans. Design Autom. Electr. Syst. Mahsa Heidari, Bijan Alizadeh
2025	J	`jnl`	Localizing Multiple Bugs in RTL Designs by Classifying Hit-Statements Using Neural Networks. IEEE Trans. Computers Mahsa Heidari, Bijan Alizadeh
2024	J	`jnl`	An FPGA-Based Hardware Architecture for P + M Class PMU Using Accuracy-Aware O-Spline Filter Selection and Modulation Detection. IEEE Trans. Instrum. Meas. Ali Falahati, Mahdieh Shamirzaee, Bijan Alizadeh
2024	J	`jnl`	Automatic Correction of Arithmetic Circuits in the Presence of Multiple Bugs by Groebner Basis Modification. ACM Trans. Design Autom. Electr. Syst. Negar Aghapour Sabbagh, Bijan Alizadeh
2024	J	`jnl`	Concealing Exposed Circuit Features Through a MaxSAT-Based Logic Locking Method. IEEE Trans. Circuits Syst. II Express Briefs Mohammad Moradi Shahmiri, Bijan Alizadeh
2024	J	`jnl`	Systematic Trojan Detection in Crypto-Systems Using the Model Checker. J. Circuits Syst. Comput. Hamed Hossein-Talaee, Ali Jahanian, Bijan Alizadeh
2023	J	`jnl`	Automatic correction of RTL designs using a lightweight partial high level synthesis. Integr. Bijan Alizadeh, Masoud Shiroei
2023	J	`jnl`	DC-PUF: Machine learning-resistant PUF-based authentication protocol using dependency chain for resource-constraint IoT devices. J. Netw. Comput. Appl. Abolfazl Sajadi, Ahmad Shabani, Bijan Alizadeh
2022	J	`jnl`	A comparative study of machine learning classifiers for secure RF-PUF-based authentication in internet of things. Microprocess. Microsystems Amir Ashtari, Ahmad Shabani, Bijan Alizadeh
2022	J	`jnl`	Hardware Patching Methodology for Neutralizing Timing Hardware Trojans Using Vulnerability Analysis and Time Borrowing Scheme. IEEE Trans. Circuits Syst. II Express Briefs Fatemeh Khormizi, Ahmad Shabani, Bijan Alizadeh
2022	J	`jnl`	Mutual Lightweight PUF-Based Authentication Scheme Using Random Key Management Mechanism for Resource-Constrained IoT Devices. ISC Int. J. Inf. Secur. Amir Ashtari, Ahmad Shabani, Bijan Alizadeh
2021	B	`conf`	Arithmetic Circuit Correction by Adding Optimized Correctors Based on Groebner Basis Computation. ETS Negar Aghapour Sabbagh, Bijan Alizadeh
2021	J	`jnl`	Enhancing Hardware Trojan Detection Sensitivity Using Partition-Based Shuffling Scheme. IEEE Trans. Circuits Syst. II Express Briefs Ahmad Shabani, Bijan Alizadeh
2021	J	`jnl`	FPGA-based Implementation of a New Data Frame Correction System for Merging Units. CoRR Mohammad Hashemi, Bijan Alizadeh
2021	J	`jnl`	SAT-Based Integrated Hardware Trojan Detection and Localization Approach Through Path-Delay Analysis. IEEE Trans. Circuits Syst. II Express Briefs Mohammad Sabri Abrebekoh, Ahmad Shabani, Bijan Alizadeh
2020	J	`jnl`	Combinational Hybrid Signal Selection With Updated Reachability Lists for Post-Silicon Debug. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Siamack BeigMohammadi, Bijan Alizadeh
2020	J	`jnl`	FPGA-Based Implementation of a Real-Time Object Recognition System Using Convolutional Neural Network. IEEE Trans. Circuits Syst. II Express Briefs Ali Azarmi Gilan, Mohammad Emad, Bijan Alizadeh
2020	J	`jnl`	Incremental SAT-Based Correction of Gate Level Circuits by Reusing Partially Corrected Circuits. IEEE Trans. Circuits Syst. Bijan Alizadeh, Yasaman Abadi
2020	J	`jnl`	PMTP: A MAX-SAT-Based Approach to Detect Hardware Trojan Using Propagation of Maximum Transition Probability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ahmad Shabani, Bijan Alizadeh
2020	J	`jnl`	PODEM: A low-cost property-based design modification for detecting Hardware Trojans in resource-constraint IoT devices. J. Netw. Comput. Appl. Ahmad Shabani, Bijan Alizadeh
2019	J	`jnl`	A Dynamic Timing Error Avoidance Technique Using Prediction Logic in High-Performance Designs. IEEE Trans. Very Large Scale Integr. Syst. Mehrnaz Ahmadi, Sahand Salamat, Bijan Alizadeh
2019	—	`conf`	A New RF-PUF Based Authentication of Internet of Things Using Random Forest Classification. ISCISC Amir Ashtari, Ahmad Shabani, Bijan Alizadeh
2019	J	`jnl`	Data-path aware high-level ECO synthesis. Integr. Masoud Shiroei, Bijan Alizadeh, Masahiro Fujita
2019	J	`jnl`	FPGA-Based Implementation of an Artificial Neural Network for Measurement Acceleration in BOTDA Sensors. IEEE Trans. Instrum. Meas. Mojtaba Abbasnezhad, Bijan Alizadeh
2019	J	`jnl`	Incremental SAT-Based Accurate Auto-Correction of Sequential Circuits Through Automatic Test Pattern Generation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Bijan Alizadeh, Seyyed Reza Sharafinejad
2018	J	`jnl`	Automatic Correction of Dynamic Power Management Architecture in Modern Processors. IEEE Trans. Very Large Scale Integr. Syst. Reza Sharafinejad, Bijan Alizadeh, Zainalabedin Navabi
2018	—	`conf`	High-Level Synthesis of Non-Rectangular Multi-Dimensional Nested Loops Using Reshaping and Vectorization. ICRC Sahand Salamat, Mohammad Reza Azarbad, Bijan Alizadeh
2018	J	`jnl`	QBF-Based Post-Silicon Debug of Speed-Paths Under Timing Variations. IEEE Trans. Circuits Syst. I Regul. Pap. Bijan Alizadeh, Mehdi Shakeri
2018	J	`jnl`	Scalable Symbolic Simulation-Based Automatic Correction of Modern Processors. IEEE Trans. Very Large Scale Integr. Syst. Fatemeh Refan, Bijan Alizadeh, Zainalabedin Navabi
2017	J	`jnl`	A Hybrid Time Borrowing Technique to Improve the Performance of Digital Circuits in the Presence of Variations. IEEE Trans. Circuits Syst. I Regul. Pap. Mehrnaz Ahmadi, Bijan Alizadeh, Behjat Forouzandeh
2017	J	`jnl`	A Resource-Limited Hardware Accelerator for Convolutional Neural Networks in Embedded Vision Applications. IEEE Trans. Circuits Syst. II Express Briefs Shayan Moini, Bijan Alizadeh, Mohammad Emad, Reza Ebrahimpour
2017	J	`jnl`	Automated Formal Equivalence Verification of Pipelined Nested Loops in Datapath Designs. CoRR Payman Behnam, Bijan Alizadeh, Sajjad Taheri
2017	J	`jnl`	Bridging Presilicon and Postsilicon Debugging by Instruction-Based Trace Signal Selection in Modern Processors. IEEE Trans. Very Large Scale Integr. Syst. Fatemeh Refan, Bijan Alizadeh, Zainalabedin Navabi
2017	J	`jnl`	Improved Range Analysis in Fixed-Point Polynomial Data-Path. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Mahdieh Grailoo, Bijan Alizadeh, Behjat Forouzandeh
2017	J	`jnl`	OptiFEX: A Framework for Exploring Area-Efficient Floating Point Expressions on FPGAs With Optimized Exponent/Mantissa Widths. IEEE Trans. Very Large Scale Integr. Syst. Alireza Mahzoon, Bijan Alizadeh
2017	—	`conf`	Reducing Search Space for Fault Diagnosis: A Probability-Based Scoring Approach. ISVLSI Hossein Sabaghian Bidgoli, Payman Behnam, Bijan Alizadeh, Zainalabedin Navabi
2017	J	`jnl`	Scalable SMT-Based Equivalence Checking of Nested Loop Pipelining in Behavioral Synthesis. ACM Trans. Design Autom. Electr. Syst. Mohammad Reza Azarbad, Bijan Alizadeh
2017	J	`jnl`	Systematic Design Space Exploration of Floating-Point Expressions on FPGA. IEEE Trans. Circuits Syst. II Express Briefs Alireza Mahzoon, Bijan Alizadeh
2017	—	`conf`	Systematic approximate logic optimization using don't care conditions. ISQED Sahand Salamat, Mehrnaz Ahmadi, Bijan Alizadeh, Masahiro Fujita
2016	J	`jnl`	A dynamic specification to automatically debug and correct various divider circuits. Integr. Mohammad Hashem Haghbayan, Bijan Alizadeh
2016	A	`conf`	Combinational trace signal selection with improved state restoration for post-silicon debug. DATE Siamack BeigMohammadi, Bijan Alizadeh
2016	—	`conf`	Formally analyzing fault tolerance in datapath designs using equivalence checking. ASP-DAC Payman Behnam, Bijan Alizadeh, Sajjad Taheri, Masahiro Fujita
2016	J	`jnl`	Genetic-Algorithm-Based FPGA Architectural Exploration Using Analytical Models. ACM Trans. Design Autom. Electr. Syst. Hossein Mehri, Bijan Alizadeh
2016	J	`jnl`	UAFEA: Unified Analytical Framework for IA/AA-Based Error Analysis of Fixed-Point Polynomial Specifications. IEEE Trans. Circuits Syst. II Express Briefs Mahdieh Grailoo, Bijan Alizadeh, Behjat Forouzandeh
2015	J	`jnl`	A Scalable Formal Debugging Approach with Auto-Correction Capability Based on Static Slicing and Dynamic Ranking for RTL Datapath Designs. IEEE Trans. Computers Bijan Alizadeh, Payman Behnam, Somayeh Sadeghi Kohan
2015	—	`conf`	A Timing Error Mitigation Technique for High Performance Designs. ISVLSI Mehrnaz Ahmadi, Bijan Alizadeh, Behjat Forouzandeh
2015	J	`jnl`	Analytical performance model for FPGA-based reconfigurable computing. Microprocess. Microsystems Hossein Mehri, Bijan Alizadeh
2015	J	`jnl`	Automatic High-Level Data-Flow Synthesis and Optimization of Polynomial Datapaths Using Functional Decomposition. IEEE Trans. Computers Samaneh Ghandali, Bijan Alizadeh, Masahiro Fujita, Zainalabedin Navabi
2015	J	`jnl`	Dynamic Flip-Flop Conversion: A Time-Borrowing Method for Performance Improvement of Low-Power Digital Circuits Prone to Variations. IEEE Trans. Very Large Scale Integr. Syst. Mehrzad Nejat, Bijan Alizadeh, Ali Afzali-Kusha
2015	J	`jnl`	Groebner basis based formal verification of large arithmetic circuits using Gaussian elimination and cone-based polynomial extraction. Microprocess. Microsystems Farimah Farahmandi, Bijan Alizadeh
2015	—	`conf`	In-Circuit Mutation-Based Automatic Correction of Certain Design Errors Using SAT Mechanisms. ATS Payman Behnam, Bijan Alizadeh
2015	—	`conf`	Low power scheduling in high-level synthesis using dual-Vth library. ISQED Samaneh Ghandali, Bijan Alizadeh, Zainalabedin Navabi
2015	—	`conf`	Multi-objective Optimization of Floating Point Arithmetic Expressions Using Iterative Factorization. ISVLSI Alireza Mahzoon, Bijan Alizadeh
2015	Misc	`conf`	Signature oriented model pruning to facilitate multi-threaded processors debugging. VTS Fatemeh Refan, Bijan Alizadeh, Zainalabedin Navabi
2015	Misc	`conf`	UPF-based formal verification of low power techniques in modern processors. VTS Reza Sharafinejad, Bijan Alizadeh, Masahiro Fujita
2014	—	`conf`	A Low-Power Enhanced Bitmask-Dictionary Scheme for Test Data Compression. ISVLSI Vahid Janfaza, Payman Behnam, Bahjat Forouzandeh, Bijan Alizadeh
2014	—	`conf`	Automated formal approach for debugging dividers using dynamic specification. DFT Mohammad Hashem Haghbayan, Bijan Alizadeh, Amir-Mohammad Rahmani, Pasi Liljeberg, Hannu Tenhunen
2014	B	`conf`	Automatic correction of certain design errors using mutation technique. ETS Payman Behnam, Bijan Alizadeh, Zainalabedin Navabi
2014	A	`conf`	Dynamic Flip-Flop conversion to tolerate process variation in low power circuits. DATE Mehrzad Nejat, Bijan Alizadeh, Ali Afzali-Kusha
2014	—	`conf`	Effective Combination of Algebraic Techniques and Decision Diagrams to Formally Verify Large Arithmetic Circuits. ISVLSI Farimah Farahmandi, Bijan Alizadeh, Zainalabedin Navabi
2014	Misc	`conf`	Formal Verification and Debugging of Array Dividers with Auto-correction Mechanism. VLSID M. H. Haghbayan, Bijan Alizadeh, Payman Behnam, Saeed Safari
2014	—	`conf`	Highly scalable, shared-memory, Monte-Carlo tree search based Blokus Duo Solver on FPGA. FPT Ehsan Qasemi, Amir Samadi, Mohammad H. Shadmehr, Bardia Azizian, Sajjad Mozaffari, Amir Shirian, Bijan Alizadeh
2014	B	`conf`	Improving polynomial datapath debugging with HEDs. ETS Somayeh Sadeghi Kohan, Payman Behnam, Bijan Alizadeh, Masahiro Fujita, Zainalabedin Navabi
2014	—	`conf`	RTL datapath optimization using system-level transformations. ISQED Samaneh Ghandali, Bijan Alizadeh, Masahiro Fujita, Zainalabedin Navabi
2013	J	`jnl`	A New Approach for Automatic Test Pattern Generation in Register Transfer Level Circuits. IEEE Des. Test Mohammad Mirzaei, Mahmoud Tabandeh, Bijan Alizadeh, Zainalabedin Navabi
2013	—	`conf`	A probabilistic approach for counterexample generation to aid design debugging. EWDTS Payman Behnam, Hossein Sabaghian Bidgoli, Bijan Alizadeh, Kamyar Mohajerani, Zainalabedin Navabi
2013	J	`jnl`	Formal equivalence verification and debugging techniques with auto-correction mechanism for RTL designs. Microprocess. Microsystems Bijan Alizadeh, Payman Behnam
2012	—	`conf`	A formal approach to debug polynomial datapath designs. ASP-DAC Bijan Alizadeh
2012	—	`conf`	A functional test generation technique for RTL datapaths. HLDVT Bijan Alizadeh, Masahiro Fujita
2012	J	`jnl`	Formal Verification and Debugging of Precise Interrupts on High Performance Microprocessors. ACM Trans. Design Autom. Electr. Syst. Bijan Alizadeh
2012	C	`conf`	Polynomial datapath synthesis and optimization based on vanishing polynomial over Z2 MEMOCODE Samaneh Ghandali, Bijan Alizadeh, Zainalabedin Navabi, Masahiro Fujita
2011	—	`conf`	Debugging and optimizing high performance superscalar out-of-order processors using formal verification techniques. ISQED Bijan Alizadeh, Masahiro Fujita
2011	C	`conf`	Early case splitting and false path detection to improve high level ATPG techniques. ISCAS Bijan Alizadeh, Masahiro Fujita
2011	—	`conf`	Modular equivalence verification of polynomial datapaths with multiple word-length operands. HLDVT Bijan Alizadeh, Masahiro Fujita
2010	—	`conf`	A debugging method for repairing post-silicon bugs of high performance processors in the fields. FPT Bijan Alizadeh, Masahiro Fujita
2010	A	`conf`	Aggressive overclocking support using a novel timing error recovery technique on FPGAs (abstract only). FPGA Amir Masoud Gharehbaghi, Bijan Alizadeh, Masahiro Fujita
2010	J	`jnl`	Coverage Driven High-Level Test Generation Using a Polynomial Model of Sequential Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Bijan Alizadeh, Mohammad Mirzaei, Masahiro Fujita
2010	—	`conf`	Guided gate-level ATPG for sequential circuits using a high-level test generation approach. ASP-DAC Bijan Alizadeh, Masahiro Fujita
2010	J	`jnl`	Modular Datapath Optimization and Verification Based on Modular-HED. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Bijan Alizadeh, Masahiro Fujita
2010	—	`conf`	Pipelined Microprocessors Optimization and Debugging. ARC Bijan Alizadeh, Amir Masoud Gharehbaghi, Masahiro Fujita
2010	A	`conf`	Polynomial datapath optimization using constraint solving and formal modelling. ICCAD Finn Haedicke, Bijan Alizadeh, Görschwin Fey, Masahiro Fujita, Rolf Drechsler
2009	J	`jnl`	A Formal Approach for Debugging Arithmetic Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Omid Sarbishei, Mahmoud Tabandeh, Bijan Alizadeh, Masahiro Fujita
2009	J	`jnl`	A Unified Framework for Equivalence Verification of Datapath Oriented Applications. IEICE Trans. Inf. Syst. Bijan Alizadeh, Masahiro Fujita
2009	C	`conf`	High-level optimization of integer multipliers over a finite bit-width with verification capabilities. MEMOCODE Omid Sarbishei, Mahmoud Tabandeh, Bijan Alizadeh, Masahiro Fujita
2009	A	`conf`	Improved heuristics for finite word-length polynomial datapath optimization. ICCAD Bijan Alizadeh, Masahiro Fujita
2009	—	`conf`	Modular arithmetic decision procedure with auto-correction mechanism. HLDVT Bijan Alizadeh, Masahiro Fujita
2009	A*	`conf`	Polynomial datapath optimization using partitioning and compensation heuristics. DAC Omid Sarbishei, Bijan Alizadeh, Masahiro Fujita
2008	C	`conf`	Arithmetic Circuits Verification without Looking for Internal Equivalences. MEMOCODE Omid Sarbishei, Bijan Alizadeh, Masahiro Fujita
2008	Misc	`conf`	Sequential Equivalence Checking Using a Hybrid Boolean-Word Level Decision Diagram. CSICC Bijan Alizadeh, Masahiro Fujita
2007	—	`conf`	A novel formal approach to generate high-level test vectors without ILP and SAT solvers. HLDVT Bijan Alizadeh, Masahiro Fujita
2007	B	`conf`	Automatic Merge-Point Detection for Sequential Equivalence Checking of System-Level and RTL Descriptions. ATVA Bijan Alizadeh, Masahiro Fujita
2006	—	`conf`	Word level functional coverage computation. ASP-DAC Bijan Alizadeh
2005	—	`conf`	Binary Taylor diagrams: an efficient implementation of Taylor expansion diagrams. ISCAS (1) Arash Hooshmand, Saeed Shamshiri, Mohammad Alisafaee, Bijan Alizadeh, Pejman Lotfi-Kamran, Mostafa Naderi, Zainalabedin Navabi
2004	—	`conf`	Property Checking based on Hierarchical Integer Equations. ACSD Bijan Alizadeh, Zainalabedin Navabi
2004	—	`conf`	Using Integer Equations to Check PSL Properties in RT Level Design. IWSOC Bijan Alizadeh, Zainalabedin Navabi
2003	—	`conf`	Using Integer Equations for High Level Formal Verification Property Checking. ISQED Bijan Alizadeh, Mohammad Reza Kakoee