Bidyut K. Bhattacharyya

27 papers Misc 1Journal 23Unranked 3

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	An Approach of ISI Elimination and High-Speed Data Reconstruction in Lossy On-Chip Serial Link. Circuits Syst. Signal Process. Anirban Tarafdar, Alak Majumder, Biman Debbarma, Bidyut K. Bhattacharyya
2024	Misc	`conf`	A Novel Approach to Control a DC-DC Converter Using its Empirical Physical Model. VLSID Sushmita Ghosh, Bidyut K. Bhattacharyya
2024	J	`jnl`	Enhancing intrusion detection using wireless sensor networks: A novel ahp-madm aggregated multiple type 3 fuzzy logic-based k-barriers prediction system. Peer Peer Netw. Appl. Anirban Tarafdar, Azharuddin Sheikh, Pinki Majumder, Abhijit Baidya, Alak Majumder, Bidyut K. Bhattacharyya, Uttam Kumar Bera
2022	J	`jnl`	A comprehensive study of different objectives and solutions of controller placement problem in software-defined networks. Trans. Emerg. Telecommun. Technol. Mili Dhar, Arindam Debnath, Bidyut K. Bhattacharyya, Mrinal Kanti Debbarma, Swapan Debbarma
2022	J	`jnl`	A cost-effective and load-balanced controller placement method in software-defined networks. Int. J. Netw. Manag. Mili Dhar, Bidyut K. Bhattacharyya, Mrinal Kanti Debbarma, Swapan Debbarma
2022	J	`jnl`	A low power and PVT variation tolerant mux-latch for serializer interface and on-chip serial link. Integr. Mithilesh Kumar, Alak Majumder, Abir J. Mondal, Arijit Raychowdhury, Bidyut K. Bhattacharyya
2022	J	`jnl`	Clock-Gated Variable Frequency Signaling to Alleviate Power Supply Noise in a Packaged IC. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Pritam Bhattacharjee, Prerna Rana, Bidyut K. Bhattacharyya, Alak Majumder
2021	J	`jnl`	A PVT aware differential delay circuit and its performance variation due to power supply noise. Integr. Anirban Tarafdar, Abir J. Mondal, Uttam Kumar Bera, Bidyut K. Bhattacharyya
2021	J	`jnl`	A Vector-Controlled Variable Delay Circuit to Develop Near-Symmetric Output Rise/Fall Time. Circuits Syst. Signal Process. Pritam Bhattacharjee, Bidyut K. Bhattacharyya, Alak Majumder
2021	J	`jnl`	A new optimization technique to solve the latency aware controller placement problem in software defined networks. Trans. Emerg. Telecommun. Technol. Mili Dhar, Bidyut K. Bhattacharyya, Mrinal Kanti Debbarma, Swapan Debbarma
2021	J	`jnl`	Buck Topology Powered Exclusively by Supercapacitor Modules - A Battery-Less Design Concept. IEEE Access Sambit Satpathy, Bidyut K. Bhattacharyya, Munesh Chandra Trivedi, Aditya Sankar Sengupta
2021	J	`jnl`	Fuzzy logic-based VANET routing method to increase the QoS by considering the dynamic nature of vehicles. Computing Arindam Debnath, Habila Basumatary, Mili Dhar, Mrinal Kanti Debbarma, Bidyut K. Bhattacharyya
2020	—	`conf`	A 90nm PVT Tolerant Current Mode Frequency Divider with Wide Locking Range. NorCAS Madhusudan Maiti, Shubhro Chakrabartty, Alaaddin Al-Shidaifat, Hanjung Song, Bidyut K. Bhattacharyya, Alak Majumder
2020	J	`jnl`	Modelling and analysis of a hybrid CS-CMOS ring VCO with wide tuning range. Microelectron. J. Madhusudan Maiti, Alak Majumder, Shubhro Chakrabartty, Hanjung Song, Bidyut K. Bhattacharyya
2020	J	`jnl`	Segmentation of images through curve fitting analysis by modified Vandermonde matrix and modified Gram-Schmidt method. IET Image Process. Kuldip Acharya, Dibyendu Ghoshal, Bidyut K. Bhattacharyya
2019	J	`jnl`	Variation Aware Design of 50-Gbit/s, 5.027-fJ/bit Serializer Using Latency Combined Mux-Dual Latch for Inter-Chip Communication. IEEE Trans. Circuits Syst. I Regul. Pap. Alak Majumder, Monalisa Das, Suraj Kumar Saw, Abir J. Mondal, Bidyut K. Bhattacharyya
2018	J	`jnl`	A New Current Profile Determination Methodology Incorporating Gating Logic to Minimize the Noise of CPU Chip by 40%. J. Circuits Syst. Comput. Nivedita Laskar, Suman Debnath, Alak Majumder, Bidyut K. Bhattacharyya
2018	J	`jnl`	Plateau limit-based tri-histogram equalisation for image enhancement. IET Image Process. Abhisek Paul, Paritosh Bhattacharya, Santi P. Maity, Bidyut K. Bhattacharyya
2018	J	`jnl`	Supercapacitors Outperform Conventional Batteries [Energy and Security]. IEEE Consumer Electron. Mag. Aditya Sankar Sengupta, Sambit Satpathy, Saraju P. Mohanty, Debasis Baral, Bidyut K. Bhattacharyya
2017	J	`jnl`	A 65 nm Design of 0.6 V/8.98 J. Low Power Electron. Alak Majumder, Abir J. Mondal, Bidyut K. Bhattacharyya
2017	—	`conf`	A 90nm Novel MUX-Dual Latch Design Approach for Gigascale Serializer Application. iNIS Monalisa Das, Alak Majumder, Abir J. Mondal, Bidyut K. Bhattacharyya
2017	—	`conf`	A Design Methodology for MOS Current Mode Logic VCO. iNIS Abir J. Mondal, Alak Majumder, Bidyut K. Bhattacharyya
2017	J	`jnl`	A mathematical formulation to design and implementation of a low voltage swing transceiver circuit. Integr. Abir J. Mondal, Alak Majumder, Bidyut K. Bhattacharyya
2017	J	`jnl`	Pay-Cloak: A Biometric Back Cover for Smartphones: Facilitating secure contactless payments and identity virtualization at low cost to end users. IEEE Consumer Electron. Mag. Alak Majumder, Joyeeta Goswami, Shirsha Ghosh, Rishu Shrivastawa, Saraju P. Mohanty, Bidyut K. Bhattacharyya
2017	J	`jnl`	Reconstruction of a single square pulse originally having 40 ps width coming from a lossy and noisy channel in a point to point interconnect. Turkish J. Electr. Eng. Comput. Sci. Alak Majumder, Bidyut K. Bhattacharyya
2017	J	`jnl`	Swing-Pay: One Card Meets All User Payment and Identity Needs: A Digital Card Module using NFC and Biometric Authentication for Peer-to-Peer Payment. IEEE Consumer Electron. Mag. Shirsha Ghosh, Alak Majumder, Joyeeta Goswami, Abhishek Kumar, Saraju P. Mohanty, Bidyut K. Bhattacharyya
2017	J	`jnl`	Threshold adjustment of receiver chip to achieve a data rate >66 Gbit/sec in point to point interconnect. Integr. Alak Majumder, Abir J. Mondal, Bidyut K. Bhattacharyya