Bibhash Sen - RankMe

68 papers C 3Misc 2Journal 39Unranked 24

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	Design and Implementation of Cost-Effective End-to-End Authentication Protocol for PUF-Enabled IoT Devices. IEEE Trans. Emerg. Top. Comput. Sourav Roy, Mahabub Hasan Mahalat, Bibhash Sen
2025	—	`conf`	Genetic Algorithm-Based Optimization of High-Density EEG Channels for Eye State Classification with a Refined Subset Approach. GECCO Companion Indrajit Dutta, Sandip Chakraborty, Sourav Samanta, Bibhash Sen
2025	—	`conf`	Synthesis and Analysis of Regular Clocking-Based Full Subtractor in QCA. ASCAT Amit Kumar Pramanik, Jayanta Pal, Bibhash Sen
2024	J	`jnl`	CAPUF: Design of a configurable circular arbiter PUF with enhanced security and hardware efficiency. Integr. Mahabub Hasan Mahalat, Shyam Subba, Anindan Mondal, Biplab K. Sikdar, Rajat Subhra Chakraborty, Bibhash Sen
2024	J	`jnl`	Identification of Hardware Trojan in Gate-Level Netlist. J. Circuits Syst. Comput. Anindan Mondal, Archisman Ghosh, Shubrojyoti Karmakar, Mahabub Hasan Mahalat, Suchismita Roy, Bibhash Sen
2024	J	`jnl`	Secure and Lightweight Authentication Protocol Using PUF for the IoT-based Wireless Sensor Network. ACM J. Emerg. Technol. Comput. Syst. Sourav Roy, Dipnarayan Das, Bibhash Sen
2024	—	`conf`	Synthesis of Fault-Tolerant QCA Logic Circuit Using Cellular Automata. ASCAT Amit Kumar Pramanik, Jayanta Pal, Bibhash Sen
2024	J	`jnl`	Towards the Detection of Hardware Trojans with Cost Effective Test Vectors using Genetic Algorithm. J. Electron. Test. Sandip Chakraborty, Archisman Ghosh, Anindan Mondal, Bibhash Sen
2023	J	`jnl`	Cost-effective synthesis of QCA logic circuit using genetic algorithm. J. Supercomput. Amit Kumar Pramanik, Mahabub Hasan Mahalat, Jayanta Pal, Seyed-Sajad Ahmadpour, Bibhash Sen
2023	—	`conf`	Design and Analysis of Regular Clock Based 2: 4 Decoder Using T-Gate in QCA. ASCAT Amit Kumar Pramanik, Sudipta Debnath, Jayanta Pal, Bibhash Sen
2023	J	`jnl`	Hardware Trojan Detection using Transition Probability with Minimal Test Vectors. ACM Trans. Embed. Comput. Syst. Anindan Mondal, Shubrojyoti Karmakar, Mahabub Hasan Mahalat, Suchismita Roy, Bibhash Sen, Anupam Chattopadhyay
2023	J	`jnl`	Non-invasive anaemia detection by examining palm pallor: A smartphone-based approach. Biomed. Signal Process. Control. Abhishek Kesarwani, Sunanda Das, Mamata Dalui, Dakshina Ranjan Kisku, Bibhash Sen, Suchismita Roy, Anupam Basu
2023	J	`jnl`	PLAKE: PUF-Based Secure Lightweight Authentication and Key Exchange Protocol for IoT. IEEE Internet Things J. Sourav Roy, Dipnarayan Das, Anindan Mondal, Mahabub Hasan Mahalat, Bibhash Sen, Biplab Sikdar
2023	J	`jnl`	Smartphone-based non-invasive haemoglobin level estimation by analyzing nail pallor. Biomed. Signal Process. Control. Sunanda Das, Abhishek Kesarwani, Mamata Dalui, Dakshina Ranjan Kisku, Bibhash Sen, Suchismita Roy, Anupam Basu
2023	J	`jnl`	Toward the Generation of Test Vectors for the Detection of Hardware Trojan Targeting Effective Switching Activity. ACM J. Emerg. Technol. Comput. Syst. Anindan Mondal, Debasish Kalita, Archisman Ghosh, Suchismita Roy, Bibhash Sen
2022	—	`conf`	A Novel Cross-Platform Physically Unclonable Function for Emerging FPGA-based IoT Devices. AsianHOST Dipnarayan Das, Sourav Roy, Mahabub Hasan Mahalat, Bibhash Sen
2022	—	`conf`	Impact of Genetic Algorithm on Low Power QCA Logic Circuit with Regular Clocking. ASCAT Amit Kumar Pramanik, Jayanta Pal, Bibhash Sen
2022	J	`jnl`	Implementation, Characterization and Application of Path Changing Switch based Arbiter PUF on FPGA as a lightweight Security Primitive for IoT. ACM Trans. Design Autom. Electr. Syst. Mahabub Hasan Mahalat, Suraj Mandal, Anindan Mondal, Bibhash Sen, Rajat Subhra Chakraborty
2022	J	`jnl`	PUF based Secure and Lightweight Authentication and Key-Sharing Scheme for Wireless Sensor Network. ACM J. Emerg. Technol. Comput. Syst. Mahabub Hasan Mahalat, Dipankar Karmakar, Anindan Mondal, Bibhash Sen
2022	—	`conf`	Performance Analysis of Regular Clocking Based Quantum-Dot Cellular Automata Logic Circuit: Fault Tolerant Approach. ACRI Amit Kumar Pramanik, Jayanta Pal, Biplab K. Sikdar, Bibhash Sen
2022	J	`jnl`	Regular clocking-based Automated Cell Placement technique in QCA targeting sequential circuit. Comput. Electr. Eng. Dhrubajyoti Bhowmik, Amit Kumar Pramanik, Jayanta Pal, Pinaki Sen, Ayush Ranjan Singh, Apu Kumar Saha, Bibhash Sen
2022	J	`jnl`	Towards the realization of regular clocking-based QCA circuits using genetic algorithm. Comput. Electr. Eng. Amit Kumar Pramanik, Dhrubajyoti Bhowmik, Jayanta Pal, Pinaki Sen, Apu Kumar Saha, Bibhash Sen
2021	J	`jnl`	CFA: Toward the Realization of Conservative Full Adder in QCA with Enhanced Reliability. J. Circuits Syst. Comput. Jayanta Pal, Mrinal Goswami, Apu Kumar Saha, Bibhash Sen
2021	J	`jnl`	CFA: Toward the Realization of Conservative Full Adder in QCA with Enhanced Reliability. J. Circuits Syst. Comput. Jayanta Pal, Mrinal Goswami, Apu Kumar Saha, Bibhash Sen
2021	J	`jnl`	Hardware Trojan Free Netlist Identification: A Clustering Approach. J. Electron. Test. Anindan Mondal, Rajesh Kumar Biswal, Mahabub Hasan Mahalat, Suchismita Roy, Bibhash Sen
2021	C	`conf`	PUF based Lightweight Authentication and Key Exchange Protocol for IoT. SECRYPT Sourav Roy, Dipnarayan Das, Anindan Mondal, Mahabub Hasan Mahalat, Suchismita Roy, Bibhash Sen
2021	J	`jnl`	Systematic cell placement in quantum-dot cellular automata embedding underlying regular clocking circuit. IET Circuits Devices Syst. Dhrubajyoti Bhowmik, Jayanta Pal, Mrinal Goswami, Pinaki Sen, Apu Kumar Saha, Bibhash Sen
2020	J	`jnl`	Design of fault tolerant majority voter for error resilient TMR targeting micro to nano scale logic. Int. J. Comput. Sci. Eng. Mrinal Goswami, Subrata Chattopadhyay, Shiv Bhushan Tripathi, Bibhash Sen
2020	J	`jnl`	In memory computation using quantum-dot cellular automata. IET Comput. Digit. Tech. Mrinal Goswami, Jayanta Pal, Mayukh Roy Choudhury, Pritam P. Chougule, Bibhash Sen
2019	—	`conf`	A Novel Test Vector Generation Method for Hardware Trojan Detection. SoCC Anindan Mondal, Mahabub Hasan Mahalat, Suraj Mandal, Suchismita Roy, Bibhash Sen
2019	—	`conf`	A Realistic Configurable Level Triggered Flip-Flop in Quantum-Dot Cellular Automata. VDAT Mrinal Goswami, Mayukh Roy Choudhury, Bibhash Sen
2019	—	`conf`	An Efficient Implementation of Arbiter PUF on FPGA for IoT Application. SoCC Mahabub Hasan Mahalat, Suraj Mandal, Anindan Mondal, Bibhash Sen
2019	J	`jnl`	An Integrated Framework for Application Independent Testing of FPGA Interconnect. J. Electron. Test. Shukla Banik, Suchismita Roy, Bibhash Sen
2019	J	`jnl`	Application-Dependent Testing of FPGA Interconnect Network. IEEE Trans. Very Large Scale Integr. Syst. Shukla Banik, Suchismita Roy, Bibhash Sen
2019	Misc	`conf`	Test Configuration Generation for Different FPGA Architectures for Application Independent Testing. VLSID Shukla Banik, Suchismita Roy, Bibhash Sen
2018	—	`conf`	A Methodology to Design Online Testable Reversible Circuits. VDAT Mrinal Goswami, Govind Raj, Aron Narzary, Bibhash Sen
2018	—	`conf`	A PUF based Light Weight Protocol for Secure WiFi Authentication of IoT devices. ISED Mahabub Hasan Mahalat, Shreya Saha, Anindan Mondal, Bibhash Sen
2018	C	`conf`	Design of Latch based Configurable Ring Oscillator PUF Targeting Secure FPGA. VLSI-SoC Mahabub Hasan Mahalat, Nikhil Ugale, Rohit Shahare, Bibhash Sen
2018	—	`conf`	XOR based Methodology to Detect Hardware Trojan utilizing the Transition Probability. ISED Anindan Mondal, Mahabub Hasan Mahalat, Anudeep Reddy Medapati, Suchismita Roy, Bibhash Sen
2017	—	`conf`	Cost effective realization of XOR logic in QCA. ISED Mrinal Goswami, Mohit Kumar, Bibhash Sen
2017	J	`jnl`	Design of Configurable Sequential Circuits in Quantum-dot Cellular Automata. CoRR Mrinal Goswami, Mayukh Roy Chowdhury, Bibhash Sen
2017	J	`jnl`	Design of Testable Adder in Quantum-dot Cellular Automata with Fault Secure Logic. Microelectron. J. Mrinal Goswami, Bibhash Sen, Rijoy Mukherjee, Biplab K. Sikdar
2017	—	`conf`	Design of reversible bidirectional logarithmic barrel shifter. ISED Mrinal Goswami, Aron Narzary, Govind Raj, Bibhash Sen
2017	J	`jnl`	Novel conservative reversible error control circuits based on molecular QCA. Int. J. Comput. Appl. Technol. Neeraj Kumar Misra, Bibhash Sen, Subodh Wairya
2017	J	`jnl`	Optimal synthesis of QCA logic circuit eliminating wire-crossings. IET Circuits Devices Syst. Rajdeep Kumar Nath, Bibhash Sen, Biplab K. Sikdar
2017	J	`jnl`	Realization of processing In-memory computing architecture using Quantum Dot Cellular Automata. Microprocess. Microsystems Pritam P. Chougule, Bibhash Sen, Tukaram D. Dongale
2017	J	`jnl`	Synthesis and Optimization of Multi-Objective Multi-Output QCA Circuit using Genetic Algorithm. CoRR Mahabub Hasan Mahalat, Mrinal Goswami, Anindan Mondal, Bibhash Sen
2017	J	`jnl`	Testable Novel Parity-Preserving Reversible Gate and Low-Cost Quantum Decoder Design in 1D Molecular-QCA. J. Circuits Syst. Comput. Neeraj Kumar Misra, Bibhash Sen, Subodh Wairya, Bandan Kumar Bhoi
2016	J	`jnl`	A Processing In-Memory Realization Using QCA: Proposal and Implementation. CoRR Pritam P. Chougule, Bibhash Sen, Rijoy Mukherjee, Vijay C. Karade, P. S. Patil, Tukaram D. Dongale, Rajanish K. Kamat
2016	—	`conf`	Design of fault tolerant majority voter for TMR circuit in QCA. VDAT Subrata Chattopadhyay, Shiv Bhushan Tripathi, Mrinal Goswami, Bibhash Sen
2016	—	`conf`	Design of low power 5-input majority voter in quantum-dot cellular automata with effective error resilience. ISED Mrinal Goswami, Bibhash Sen, Biplab K. Sikdar
2016	J	`jnl`	On the reliability of majority logic structure in quantum-dot cellular automata. Microelectron. J. Bibhash Sen, Yashraj Sahu, Rijoy Mukherjee, Rajdeep Kumar Nath, Biplab K. Sikdar
2016	J	`jnl`	Processing In-memory realization using Quantum Dot Cellular Automata. CoRR Pritam P. Chougule, Bibhash Sen, Tukaram D. Dongale
2016	Misc	`conf`	Towards Designing Reliable Universal QCA Logic in the Presence of Cell Deposition Defect. VLSID Bibhash Sen, Rajdeep Kumar Nath, Rijoy Mukherjee, Yashraj Sahu, Biplab K. Sikdar
2015	—	`conf`	Fault masking in Quantum-dot cellular automata using prohibitive logic circuit. VDAT Rajdeep Kumar Nath, Bibhash Sen, Rachit Daga, Nilesh Chakraborty, Harsh Tibrewal, Biplab K. Sikdar
2015	J	`jnl`	Handwritten Devanagari Script Segmentation: A non-linear Fuzzy Approach. CoRR Ram Sarkar, Bibhash Sen, Nibaran Das, Subhadip Basu
2015	J	`jnl`	Towards modular design of reliable quantum-dot cellular automata logic circuit using multiplexers. Comput. Electr. Eng. Bibhash Sen, Mrinal Goswami, Subhra Mazumdar, Biplab K. Sikdar
2015	J	`jnl`	Towards the hierarchical design of multilayer QCA logic circuit. J. Comput. Sci. Bibhash Sen, Anirban Nag, Asmit De, Biplab K. Sikdar
2014	—	`conf`	Design of Fault Tolerant Universal Logic in QCA. ISED Bibhash Sen, Rijoy Mukherjee, Rajdeep Kumar Nath, Biplab K. Sikdar
2014	J	`jnl`	Efficient design of parity preserving logic in quantum-dot cellular automata targeting enhanced scalability in testing. Microelectron. J. Bibhash Sen, Manojit Dutta, Biplab K. Sikdar
2014	J	`jnl`	Modular Design of testable reversible ALU by QCA multiplexer with increase in programmability. Microelectron. J. Bibhash Sen, Manojit Dutta, Mrinal Goswami, Biplab K. Sikdar
2014	J	`jnl`	Realizing Reversible Computing in QCA Framework Resulting in Efficient Design of Testable ALU. ACM J. Emerg. Technol. Comput. Syst. Bibhash Sen, Manojit Dutta, Samik Some, Biplab K. Sikdar
2013	—	`conf`	Design of Sequential Circuits in Multilayer QCA Structure. ISED Bibhash Sen, Mrinal Goswami, Samik Some, Biplab K. Sikdar
2012	—	`conf`	An Efficient Multiplexer in Quantum-dot Cellular Automata. VDAT Bibhash Sen, Manojit Dutta, Divyam Saran, Biplab K. Sikdar
2012	—	`conf`	Design of Fault Tolerant Reversible Arithmetic Logic Unit in QCA. ISED Bibhash Sen, Manojit Dutta, Debajyoty Banik, Dipak K. Singh, Biplab K. Sikdar
2011	—	`conf`	Synthesis of Reversible Universal Logic around QCA with Online Testability. ISED Bibhash Sen, Divyam Saran, Mousumi Saha, Biplab K. Sikdar
2010	C	`conf`	Design of Testable Universal Logic Gate Targeting Minimum Wire-Crossings in QCA Logic Circuit. DSD Bibhash Sen, Anik Sengupta, Mamata Dalui, Biplab K. Sikdar
2010	—	`conf`	Introducing universal QCA logic gate for synthesizing symmetric functions with minimum wire-crossings. ICWET Bibhash Sen, Mamata Dalui, Biplab K. Sikdar