Bi Wu

52 papers A* 4A 1C 5Journal 28Unranked 14
YearRankTypeTitle / Venue / Authors
2026 J jnl
A quality-configurable approximate cache design based on NAND-like SOT MRAM with high energy efficiency.
Integr.
Zhengyi Hou, Luyao Shi, Yan Qiao, Bi Wang, Bi Wu, Lirida Naviner, Zhaohao Wang
2026 — conf
BIHDC: A Retrainable Fully-Binary Hyperdimensional Computing Accelerator for Edge FPGAs.
ASP-DAC
Changzhen Han, Ke Chen, Bi Wu, Chenggang Yan, Weiqiang Liu
2025 J jnl
HDANNS: In-Memory Hyperdimensional Computing for Billion-Scale Approximate Nearest Neighbour Search Acceleration.
IEEE Trans. Circuits Syst. Artif. Intell.
Tianyang Yu, Bi Wu, Ke Chen, Chenggang Yan, Gong Zhang, Weiqiang Liu
2025 C conf
High-Performance Co-Processing Architecture Using SOT-MRAM-Based In-memory Computing Scheme.
ISCAS
Kai Tian, Bi Wu, Ke Chen, Weiqiang Liu
2025 J jnl
LAHDC: Logic-Aggregation-Based Query for Embedded Hyperdimensional Computing Accelerator.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Tianyang Yu, Bi Wu, Ke Chen, Gong Zhang, Weiqiang Liu
2025 C conf
Learning-Based Realtime Synthetic Aperture Radar Imaging for Embedded System on Satellite.
ISCAS
Tianyang Yu, Bi Wu, Weiqiang Liu
2025 A* conf
MIRACLE: Multimodal Information Retrieval via a Combined In-Memory Processing and Content Addressable Memory Approach.
DAC
Xuehui Liu, Xueyan Wang, Tianyang Yu, Chen Cheng, Shuo Ran, Bi Wu, Xiaotao Jia, Weiqiang Liu, Gang Qu, Weisheng Zhao
2025 A* conf
PreDAC: An Efficient Framework of Pre-Refining Enhanced Design Space Exploration for Approximate Computing.
DAC
Ziying Cui, Ke Chen, Bi Wu, Yu Gong, Chenggang Yan, Weiqiang Liu
2025 J jnl
SS-MRAM: A Segment-Based Search Scheme With Configurable Matching for High-Accuracy Hyperdimensional Computing in CAM Applications.
IEEE Trans. Circuits Syst. I Regul. Pap.
Bi Wu, Yang Hu, Shuo Ran, Xun Zhang, Ke Chen, Chenggang Yan, Weiqiang Liu
2024 A* conf
A Combined Content Addressable Memory and In-Memory Processing Approach for k-Clique Counting Acceleration.
DAC
Xidi Ma, Weichen Zhang, Xueyan Wang, Tianyang Yu, Bi Wu, Gang Qu, Weisheng Zhao
2024 J jnl
A Potential Enabler for High-Performance In-Memory Multi-Bit Arithmetic Schemes With Unipolar Switching SOT-MRAM.
IEEE Trans. Circuits Syst. I Regul. Pap.
Haonan Zhu, Bi Wu, Tianyang Yu, Ke Chen, Chenggang Yan, Weiqiang Liu
2024 C conf
A Time Efficient Comprehensive Model of Approximate Multipliers for Design Space Exploration.
ARITH
Ziying Cui, Ke Chen, Bi Wu, Chenggang Yan, Yu Gong, Weiqiang Liu
2024 J jnl
AttnACQ: Attentioned-AutoCorrelation-Based Query for Hyperdimensional Associative Memory.
IEEE Trans. Circuits Syst. II Express Briefs
Tianyang Yu, Bi Wu, Ke Chen, Gong Zhang, Weiqiang Liu
2024 J jnl
Edge-Side Fine-Grained Sparse CNN Accelerator With Efficient Dynamic Pruning Scheme.
IEEE Trans. Circuits Syst. I Regul. Pap.
Bi Wu, Tianyang Yu, Ke Chen, Weiqiang Liu
2024 J jnl
Fully Learnable Hyperdimensional Computing Framework With Ultratiny Accelerator for Edge-Side Applications.
IEEE Trans. Computers
Tianyang Yu, Bi Wu, Ke Chen, Gong Zhang, Weiqiang Liu
2024 C conf
Most Significant One-Driven Shifting Dynamic Efficient Multipliers for Large Language Models.
ISCAS
Bin Gong, Ke Chen, Pengfei Huang, Bi Wu, Weiqiang Liu
2024 J jnl
Toward Efficient Retraining: A Large-Scale Approximate Neural Network Framework With Cross-Layer Optimization.
IEEE Trans. Very Large Scale Integr. Syst.
Tianyang Yu, Bi Wu, Ke Chen, Chenggang Yan, Weiqiang Liu
2023 — conf
A High Accuracy and Hardware Efficient Adaptive Filter Design with Approximate Computing.
MWSCAS
Wenzhuo Xie, Chenggang Yan, Hanghang Wang, Ke Chen, Bi Wu, Chenghua Wang, Weiqiang Liu
2023 J jnl
A Survey of MRAM-Centric Computing: From Near Memory to In Memory.
IEEE Trans. Emerg. Top. Comput.
Yueting Li, Tianshuo Bai, Xinyi Xu, Yundong Zhang, Bi Wu, Hao Cai, Biao Pan, Weisheng Zhao
2023 J jnl
An Energy-Efficient Computing-in-Memory (CiM) Scheme Using Field-Free Spin-Orbit Torque (SOT) Magnetic RAMs.
IEEE Trans. Emerg. Top. Comput.
Bi Wu, Haonan Zhu, Dayane Reis, Zhaohao Wang, Ying Wang, Ke Chen, Weiqiang Liu, Fabrizio Lombardi, Xiaobo Sharon Hu
2023 J jnl
Hardware Efficient Successive-Cancellation Polar Decoders Using Approximate Computing.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Chenggang Yan, Yuxuan Cui, Ke Chen, Bi Wu, Weiqiang Liu
2023 — conf
Hardware-Efficient Accurate and Approximate FPGA Multipliers for Error-Tolerant Applications.
MWSCAS
Haonan Wang, Ke Chen, Chenggang Yan, Bi Wu, Weiqiang Liu
2023 J jnl
MLiM: High-Performance Magnetic Logic in-Memory Scheme With Unipolar Switching SOT-MRAM.
IEEE Trans. Circuits Syst. I Regul. Pap.
Bi Wu, Haonan Zhu, Ke Chen, Chenggang Yan, Weiqiang Liu
2023 — conf
VLCP: A High-Performance FPGA-based CNN Accelerator with Vector-level Cluster Pruning.
NANOARCH
Shuo Ran, Bi Wu, Ke Chen, Weiqiang Liu
2022 — conf
A High-Speed CNN Hardware Accelerator with Regular Pruning.
ISQED
Yuan Song, Bi Wu, Tian Yuan, Weiqiang Liu
2022 — conf
An Energy-Efficient Approximate Floating-Point Multipliers for Wireless Communications.
APCCAS
Jipeng Ge, Chenggang Yan, Xuan Zhao, Ke Chen, Bi Wu, Weiqiang Liu
2022 — conf
An Energy-efficient and High-precision Approximate MAC with Distributed Arithmetic Circuits.
ACM Great Lakes Symposium on VLSI
Ziying Cui, Ke Chen, Bi Wu, Chenggang Yan, Weiqiang Liu
2022 — conf
Capacity-oriented High-performance NV-TCAM Leveraging Hybrid MRAM Scheme.
NANOARCH
Didi Zhang, Bi Wu, Haonan Zhu, Weiqiang Liu
2022 — conf
Data Stream Oriented Fine-grained Sparse CNN Accelerator with Efficient Unstructured Pruning Strategy.
ACM Great Lakes Symposium on VLSI
Tianyang Yu, Bi Wu, Ke Chen, Chenggang Yan, Weiqiang Liu
2022 J jnl
Editorial Special Issue on Circuits and Systems for Emerging Computing Paradigms.
IEEE Trans. Circuits Syst. I Regul. Pap.
Shanshan Liu, Bi Wu, Ke Chen, Weiqiang Liu, Máire O'Neill, Fabrizio Lombardi
2022 C conf
Energy-efficient Oriented Approximate Quantization Scheme for Fine-Grained Sparse Neural Network Acceleration.
ICCD
Tianyang Yu, Bi Wu, Ke Chen, Chenggang Yan, Weiqiang Liu
2022 J jnl
GBC: An Energy-Efficient LSTM Accelerator With Gating Units Level Balanced Compression Strategy.
IEEE Trans. Circuits Syst. I Regul. Pap.
Bi Wu, Zhengkuan Wang, Ke Chen, Chenggang Yan, Weiqiang Liu
2022 — conf
HEADiv: A High-accuracy Energy-efficient Approximate Divider with Error Compensation.
NANOARCH
Hanghang Wang, Ke Chen, Bi Wu, Chenghua Wang, Weiqiang Liu, Fabrizio Lombardi
2022 — conf
High-performance STT-MRAM Logic-in-Memory Scheme Utilizing Data Read Features.
NANOARCH
Kai Liu, Bi Wu, Haonan Zhu, Weiqiang Liu
2022 — conf
Low-cost stochastic number generator based on MRAM for stochastic computing.
NANOARCH
You Wang, Bi Wu, Hao Cai, Weiqiang Liu
2021 J jnl
A NAND-SPIN-Based Magnetic ADC.
IEEE Trans. Circuits Syst. II Express Briefs
Bi Wu, Zhaohao Wang, Yuxuan Li, Ying Wang, Dijun Liu, Weisheng Zhao, Xiaobo Sharon Hu
2021 J jnl
An Energy Efficient Accelerator for Bidirectional Recurrent Neural Networks (BiRNNs) Using Hybrid-Iterative Compression With Error Sensitivity.
IEEE Trans. Circuits Syst. I Regul. Pap.
Guocai Nan, Zhengkuan Wang, Chenghua Wang, Bi Wu, Zhican Wang, Weiqiang Liu, Fabrizio Lombardi
2020 J jnl
A Comparative Cross-layer Study on Racetrack Memories: Domain Wall vs Skyrmion.
ACM J. Emerg. Technol. Comput. Syst.
Wang Kang, Bi Wu, Xing Chen, Daoqian Zhu, Zhaohao Wang, Xichao Zhang, Yan Zhou, Youguang Zhang, Weisheng Zhao
2020 J jnl
A Novel High Performance and Energy Efficient NUCA Architecture for STT-MRAM LLCs With Thermal Consideration.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Bi Wu, Pengcheng Dai, Yuanqing Cheng, Ying Wang, Jianlei Yang, Zhaohao Wang, Dijun Liu, Weisheng Zhao
2020 J jnl
Bulkyflip: A NAND-SPIN-Based Last-Level Cache With Bandwidth-Oriented Write Management Policy.
IEEE Trans. Circuits Syst. I Regul. Pap.
Bi Wu, Weisheng Zhao, Xiaobo Sharon Hu, Pengcheng Dai, Zhaohao Wang, Chao Wang, Ying Wang, Jianlei Yang, Yuanqing Cheng, Dijun Liu, Youguang Zhang
2020 J jnl
Field-Free 3T2SOT MRAM for Non-Volatile Cache Memories.
IEEE Trans. Circuits Syst.
Bi Wu, Chao Wang, Zhaohao Wang, Ying Wang, Deming Zhang, Dijun Liu, Youguang Zhang, Xiaobo Sharon Hu
2020 J jnl
Write Back Energy Optimization for STT-MRAM-based Last-level Cache with Data Pattern Characterization.
ACM J. Emerg. Technol. Comput. Syst.
Jiacheng Ni, Keren Liu, Bi Wu, Weisheng Zhao, Yuanqing Cheng, Xiaolong Zhang, Ying Wang
2019 J jnl
An Adaptive Thermal-Aware ECC Scheme for Reliable STT-MRAM LLC Design.
IEEE Trans. Very Large Scale Integr. Syst.
Bi Wu, Beibei Zhang, Yuanqing Cheng, Ying Wang, Dijun Liu, Weisheng Zhao
2019 J jnl
Erase-hidden and Drivability-improved Magnetic Non-Volatile Flip-Flops with NAND-SPIN Devices.
CoRR
Ziyi Wang, Zhaohao Wang, Yansong Xu, Bi Wu, Weisheng Zhao
2019 J jnl
Novel Radiation Hardening Read/Write Circuits Using Feedback Connections for Spin-Orbit Torque Magnetic Random Access Memory.
IEEE Trans. Circuits Syst. I Regul. Pap.
Bi Wang, Zhaohao Wang, Bi Wu, Yumeng Bai, Kaihua Cao, Yuanfu Zhao, Youguang Zhang, Weisheng Zhao
2019 J jnl
Ultra-Dense Ring-Shaped Racetrack Memory Cache Design.
IEEE Trans. Circuits Syst. I Regul. Pap.
Guanda Wang, Yue Zhang, Beibei Zhang, Bi Wu, Jiang Nan, Xueying Zhang, Zhizhong Zhang, Jacques-Olivier Klein, Dafine Ravelosona, Zhaohao Wang, Youguang Zhang, Weisheng Zhao
2018 J jnl
An Adaptive 3T-3MTJ Memory Cell Design for STT-MRAM-Based LLCs.
IEEE Trans. Very Large Scale Integr. Syst.
Linuo Xue, Bi Wu, Beibei Zhang, Yuanqing Cheng, Peiyuan Wang, Chando Park, Jimmy J. Kan, Seung-Hyuk Kang, Yuan Xie
2018 — conf
Write Energy Optimization for STT-MRAM Cache with Data Pattern Characterization.
ISVLSI
Bi Wu, Xiaolong Zhang, Yuanqing Cheng, Zhaohao Wang, Dijun Liu, Youguang Zhang, Weisheng Zhao
2017 A conf
Thermosiphon: A thermal aware NUCA architecture for write energy reduction of the STT-MRAM based LLCs.
ICCAD
Bi Wu, Yuanqing Cheng, Pengcheng Dai, Jianlei Yang, Youguang Zhang, Dijun Liu, Ying Wang, Weisheng Zhao
2016 A* conf
PDS: pseudo-differential sensing scheme for STT-MRAM.
DAC
Wang Kang, Tingting Pang, Bi Wu, Weifeng Lv, Youguang Zhang, Guangyu Sun, Weisheng Zhao
2016 J jnl
Temperature Impact Analysis and Access Reliability Enhancement for 1T1MTJ STT-RAM.
IEEE Trans. Reliab.
Bi Wu, Yuanqing Cheng, Jianlei Yang, Aida Todri-Sanial, Weisheng Zhao
2015 — conf
An architecture-level cache simulation framework supporting advanced PMA STT-MRAM.
NANOARCH
Bi Wu, Yuanqing Cheng, Ying Wang, Aida Todri-Sanial, Guangyu Sun, Lionel Torres, Weisheng Zhao