Bharat L. Bhuva

40 papers C 1Journal 10Unranked 29

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	Power and SER Performance of Flip-Flop Cells with Low-Leakage Options. IRPS Nicholas J. Pieper, Y. Xiong, Jenna B. Kronenberg, R. Fung, Dennis R. Ball, Bharat L. Bhuva
2025	—	`conf`	Power-Aware Mitigation of Logic Soft Error Rates at the 3-nm Bulk FinFET Node. IRPS Jenna B. Kronenberg, Y. Xiong, Nicholas J. Pieper, Dennis R. Ball, Bharat L. Bhuva
2024	—	`conf`	Multiple Bit Upsets in Register Circuits at the 5-nm Bulk FinFET Node. IRPS Yoni Xiong, Nicholas J. Pieper, Jenna B. Kronenberg, Dennis R. Ball, Megan Casey, Bharat L. Bhuva
2024	—	`conf`	Scaling Trends and Bias Dependence of SRAM SER from 16-nm to 3-nm FinFET. IRPS Balaji Narasimham, A-R. Montoya, C. Paone, T. Riehle, Mike Smith, Liming Tsau, Dennis R. Ball, Bharat L. Bhuva
2024	—	`conf`	Single-Event Performance of Flip Flop Designs at the 5-nm Bulk FinFET Node at Near-Threshold Supply Voltages. IRPS Jenna B. Kronenberg, Yoni Xiong, Nicholas J. Pieper, Dennis R. Ball, Bharat L. Bhuva
2024	—	`conf`	Total-Ionizing Dose Damage from X-Ray PCB Inspection Systems. IRPS Nicholas J. Pieper, M. Chun, Yoni Xiong, H. M. Dattilo, Jenna B. Kronenberg, Sanghyeon Baeg, Shi-Jie Wen, Rita Fung, D. Chan, C. Escobar, Bharat L. Bhuva
2023	—	`conf`	Effects of Collected Charge and Drain Area on SE Response of SRAMs at the 5-nm FinFET Node. IRPS Nicholas J. Pieper, Yoni Xiong, Dennis R. Ball, J. Pasternak, Bharat L. Bhuva
2023	—	`conf`	Soft Error Rate Predictions for Terrestrial Neutrons at the 3-nm Bulk FinFET Technology. IRPS Yoni Xiong, Yueh Chiang, Nicholas J. Pieper, Dennis R. Ball, Bharat L. Bhuva
2022	—	`conf`	Single-Event Latchup Vulnerability at the 7-nm FinFET Node. IRPS Nicholas J. Pieper, Yoni Xiong, Alexandra Feeley, Dennis R. Ball, Bharat L. Bhuva
2022	—	`conf`	Soft Error Characterization of D-FFs at the 5-nm Bulk FinFET Technology for the Terrestrial Environment. IRPS Yoni Xiong, Alexandra Feeley, Nicholas J. Pieper, Dennis R. Ball, Balaji Narasimham, John Brockman, N. A. Dodds, S. A. Wender, Shi-Jie Wen, Rita Fung, Bharat L. Bhuva
2021	—	`conf`	Effects of Temperature and Supply Voltage on Soft Errors for 7-nm Bulk FinFET Technology. IRPS Alexandra Feeley, Yoni Xiong, Bharat L. Bhuva, Balaji Narasimham, Shi-Ji Wen, Rita Fung
2021	—	`conf`	Frequency, LET, and Supply Voltage Dependence of Logic Soft Errors at the 7-nm Node. IRPS Yoni Xiong, Alexandra Feeley, Lloyd W. Massengill, Bharat L. Bhuva, Shi-Jie Wen, Rita Fung
2021	—	`conf`	Scaling Trends in the Soft Error Rate of SRAMs from Planar to 5-nm FinFET. IRPS Balaji Narasimham, Vikas Chaudhary, Mike Smith, Liming Tsau, Dennis R. Ball, Bharat L. Bhuva
2020	—	`conf`	High-Current State triggered by Operating-Frequency Change. IRPS Lyuan Xu, Jingchen Cao, Shi-Jie Wen, Rita Fung, Jamie Markevitch, Dennis R. Ball, Bharat L. Bhuva
2020	—	`conf`	Temperature Dependence of Single-Event Transient Pulse Widths for 7-nm Bulk FinFET Technology. IRPS Jingchen Cao, Lyuan Xu, Shi-Jie Wen, Rita Fung, Balaji Narasimham, Lloyd W. Massengill, Bharat L. Bhuva
2020	—	`conf`	Thermal Neutron Induced Soft Errors in 7-nm Bulk FinFET Node. IRPS Lyuan Xu, Jingchen Cao, John Brockman, Carlo Cazzaniga, Christopher Frost, Shi-Jie Wen, Rita Fung, Bharat L. Bhuva
2019	—	`conf`	Alpha Particle Soft-Error Rates for D-FF Designs in 16-Nm and 7-Nm Bulk FinFET Technologies. IRPS Jingchen Cao, Lyuan Xu, Bharat L. Bhuva, Shi-Jie Wen, Richard Wong, Balaji Narasimham, Lloyd W. Massengill
2019	—	`conf`	Neutron Beam Attenuation Through Semiconductor Devices During SEU Testing. IRPS S. A. Wender, J. M. O'Donnell, Lukas Zavorka, Bharat L. Bhuva
2019	—	`conf`	Single-Event Upset Responses of Dual- and Triple-Well D Flip-Flop Designs in 7-nm Bulk FinFET Technology. IRPS Lyuan Xu, Jingchen Cao, Bharat L. Bhuva, Indranil Chatterjee, Shi-Jie Wen, Richard Wong, Lloyd W. Massengill
2019	—	`conf`	Soft Error Performance of High-Speed Pulsed-DICE-Latch Design in 16 nm and 7 nm FinFET Processes. IRPS Balaji Narasimham, K. Chandrasekharan, J. K. Wang, Bharat L. Bhuva
2018	J	`jnl`	A TCAD evaluation of a single Bulk-BICS with integrative memory cell. Microelectron. J. Alexandre Simionovski, Gilson I. Wirth, Ronald D. Schrimpf, Bharat L. Bhuva
2018	—	`conf`	Designing soft-error-aware circuits with power and speed optimization. IRPS H. Jiang, H. Zhang, Balaji Narasimham, Lloyd W. Massengill, Bharat L. Bhuva
2018	—	`conf`	Evaluation on flip-flop physical unclonable functions in a 14/16-nm bulk FinFET technology. IRPS H. Zhang, H. Jiang, M. R. Eaker, Kurt J. Lezon, Balaji Narasimham, Nihaar N. Mahatme, Lloyd W. Massengill, Bharat L. Bhuva
2018	—	`conf`	Impact of supply voltage and particle LET on the soft error rate of logic circuits. IRPS Hui Jiang, H. Zhang, R. C. Harrington, J. A. Maharrey, J. S. Kauppila, Lloyd W. Massengill, Bharat L. Bhuva
2018	—	`conf`	Single-event effects on optical transceiver. IRPS Kurt J. Lezon, Shi-Jie Wen, Y.-F. Dan, Richard Wong, Bharat L. Bhuva
2016	C	`conf`	Single-event performance of differential flip-flop designs and hardening implication. IOLTS Rongmei Chen, Enxia Zhang, Bharat L. Bhuva
2015	—	`conf`	Influence of supply voltage on the multi-cell upset soft error sensitivity of dual- and triple-well 28 nm CMOS SRAMs. IRPS Balaji Narasimham, Jung K. Wang, Narayana Vedula, Saket Gupta, Brandon Bartz, Carl Monzel, Indranil Chatterjee, Bharat L. Bhuva, Ronald D. Schrimpf, Robert A. Reed
2015	—	`conf`	Multi-cell soft errors at the 16-nm FinFET technology node. IRPS N. Tam, Bharat L. Bhuva, Lloyd W. Massengill, Dennis R. Ball, Michael W. McCurdy, Michael L. Alles, Indranil Chatterjee
2015	—	`conf`	Terrestrial SER characterization for nanoscale technologies: A comparative study. IRPS Nihaar N. Mahatme, Bharat L. Bhuva, Nelson J. Gaspard, T. Assis, Y. Xu, P. Marcoux, M. Vilchis, Balaji Narasimham, A. Shih, Shi-Jie Wen, Rick Wong, N. Tam, M. Shroff, S. Koyoma, A. Oates
2014	J	`jnl`	Single-Event Transient Measurements on a DC/DC Pulse Width Modulator Using Heavy Ion, Proton, and Pulsed Laser. J. Electron. Test. Yi Ren, Anlin He, Shuting Shi, Gang Guo, Li Chen, Shi-Jie Wen, Richard Wong, N. W. van Vonno, Bharat L. Bhuva
2013	J	`jnl`	A Bulk Built-In Voltage Sensor to Detect Physical Location of Single-Event Transients. J. Electron. Test. Zhichao Zhang, Yi Ren, Li Chen, Nelson J. Gaspard, Arthur F. Witulski, W. Timothy Holman, Bharat L. Bhuva, Shi-Jie Wen, Ramaswami Sammynaiken
2013	J	`jnl`	An efficient technique to select logic nodes for single event transient pulse-width reduction. Microelectron. Reliab. Nihaar N. Mahatme, Indranil Chatterjee, Akash Patki, Daniel B. Limbrick, Bharat L. Bhuva, Ronald D. Schrimpf, William H. Robinson
2012	J	`jnl`	Performance, Metastability, and Soft-Error Robustness Trade-offs for Flip-Flops in 40 nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. David Rennie, David Li, Manoj Sachdev, Bharat L. Bhuva, Srikanth Jagannathan, Shi-Jie Wen, Richard Wong
2012	J	`jnl`	Single-Event Effects Analysis of a Pulse Width Modulator IC in a DC/DC Converter. J. Electron. Test. Yi Ren, L. Fan, Li Chen, Shi-Jie Wen, Richard Wong, N. W. van Vonno, Arthur F. Witulski, Bharat L. Bhuva
2011	—	`conf`	Impact of Synthesis Constraints on Error Propagation Probability of Digital Circuits. DFT Daniel B. Limbrick, Suge Yue, William H. Robinson, Bharat L. Bhuva
2011	—	`conf`	Performance, metastability and soft-error robustness tradeoffs for flip-flops in 40nm CMOS. CICC David Rennie, David Li, Manoj Sachdev, Bharat L. Bhuva, Srikanth Jagannathan, Shi-Jie Wen, Rick Wong
2008	J	`jnl`	Design Technique for Mitigation of Soft Errors in Differential Switched-Capacitor Circuits. IEEE Trans. Circuits Syst. II Express Briefs Patrick R. Fleming, Brian D. Olson, W. Timothy Holman, Bharat L. Bhuva, Lloyd W. Massengill
1993	J	`jnl`	Statistical degradation analysis of digital CMOS IC's. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Venkata S. Rangavajjhala, Bharat L. Bhuva, Sherra E. Kerns
1992	J	`jnl`	Multi-level qualitative reasoning applied to CMOS digital circuits. Artif. Intell. Eng. Neeraj Kaul, Gautam Biswas, Bharat L. Bhuva
1989	J	`jnl`	Switch-level simulation of total dose effects on CMOS VLSI circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Bharat L. Bhuva, John J. Paulos, Ronald S. Gyurcsik, Sherra E. Kerns