Bevan M. Baas - RankMe

79 papers A* 1B 1C 14Misc 5Journal 30Unranked 28

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	Optimizing Internal Data Width in FFT Accelerators for Signal-to-Noise Ratio and Area Efficiency. IEEECONF Daniel A. Chevy, Bevan M. Baas
2025	—	`conf`	Regular Expression Processing on A Many-Core Platform. MCSoC Sagar Sajeev, Bevan M. Baas
2025	—	`conf`	Scalable Discrete Cosine Transform Engines on a Many-Core Platform. MCSoC Michael Wang, Bevan M. Baas
2023	—	`conf`	A Scalable JPEG Encoder on a Many-Core Array. MCSoC Thomas Abbott, Bevan M. Baas
2023	J	`jnl`	Energy-efficient canonical Huffman decoders on many-core processor arrays and FPGAs. Integr. Satyabrata Sarangi, Bevan M. Baas
2023	—	`conf`	Many-Core Display Stream Compression Decoders With Simplified Pixel Prediction. MWSCAS Shifu Wu, Bevan M. Baas
2022	C	`conf`	A Low-Overhead Method for the Accurate Estimation of the Maximum Operating Clock Frequency. VLSI-SoC Brent Bohnenstiehl, Aaron Stillmaker, Timothy Andreas, Bevan M. Baas
2022	C	`conf`	Architecture and 28 nm CMOS Design of a 1886 MBin/sec Context-Adaptive Binary Arithmetic Coder (CABAC) Encoder. VLSI-SoC Renjie Chen, Aaron Stillmaker, Bevan M. Baas
2022	—	`conf`	Efficient and High-Performance Sparse Matrix-Vector Multiplication on a Many-Core Array. MCSoC Peiyao Shi, Aaron Stillmaker, Bevan M. Baas
2021	—	`conf`	A 1448-Mpixel/s, 84-pJ/Pixel Display Stream Compression Encoder in 28 nm for 4K Video Resolution. A-SSCC Shifu Wu, K. De Silva, Snehlata Gutgutia, Bevan M. Baas, Massimo Alioto
2021	—	`conf`	Canonical Huffman Decoder on Fine-grain Many-core Processor Arrays. ASP-DAC Satyabrata Sarangi, Bevan M. Baas
2021	J	`jnl`	DeepScaleTool : A Tool for the Accurate Estimation of Technology Scaling in the Deep-Submicron Era. CoRR Satyabrata Sarangi, Bevan M. Baas
2021	C	`conf`	DeepScaleTool: A Tool for the Accurate Estimation of Technology Scaling in the Deep-Submicron Era. ISCAS Satyabrata Sarangi, Bevan M. Baas
2021	J	`jnl`	Display Stream Compression Decoders for Fine-Grained Many-Core Processor Arrays. IEEE Trans. Circuits Syst. II Express Briefs Shifu Wu, Bevan M. Baas
2020	J	`jnl`	Correction to: Guest Editorial: JSPS Special Issue on 2018 IEEE Signal Processing Systems (SiPS) Workshop. J. Signal Process. Syst. Tokunbo Ogunfunmi, John McAllister, Bevan M. Baas, Mrityunjoy Chakraborty
2020	J	`jnl`	Guest Editorial: JSPS Special Issue on 2018 IEEE Signal Processing Systems (SiPS) Workshop. J. Signal Process. Syst. Tokunbo Ogunfunmi, John McAllister, Bevan M. Baas, Mrityunjoy Chakraborty
2020	—	`conf`	Indexed Color History Many-Core Engines for Display Stream Compression Decoders. ICECS Shifu Wu, Bevan M. Baas
2020	J	`jnl`	Scalable energy-efficient parallel sorting on a fine-grained many-core processor array. J. Parallel Distributed Comput. Aaron Stillmaker, Brent Bohnenstiehl, Lucas Stillmaker, Bevan M. Baas
2019	J	`jnl`	Corrigendum to "Scaling equations for the accurate prediction of CMOS device performance from 180 nm to 7 nm" [Integr. VLSI J. 58. (2017) 74-81]. Integr. Aaron Stillmaker, Bevan M. Baas
2018	—	`conf`	A Low-Cost Slice Interleaving DSC Decoder Architecture for Real-Time 8K Video Decoding. MWSCAS Shifu Wu, Bevan M. Baas
2018	Misc	`conf`	Display Stream Compression Encoder Architectures for Real-time 4K and 8K Video Encoding. ACSSC Shifu Wu, Snehlata Gutgutia, Massimo Alioto, Bevan M. Baas
2017	—	`conf`	A configurable H.265-compatible motion estimation accelerator architecture for realtime 4K video encoding in 65 nm CMOS. DSC Michael Braly, Aaron Stillmaker, Bevan M. Baas
2017	J	`jnl`	Editorial. IEEE Trans. Very Large Scale Integr. Syst. Krishnendu Chakrabarty, Massimo Alioto, Bevan M. Baas, Chirn Chye Boon, Meng-Fan Chang, Naehyuck Chang, Yao-Wen Chang, Chip-Hong Chang, Shih-Chieh Chang, Poki Chen, Masud H. Chowdhury, Pasquale Corsonello, Ibrahim Abe M. Elfadel, Said Hamdioui, Masanori Hashimoto, Tsung-Yi Ho, Houman Homayoun, Yuh-Shyan Hwang, Rajiv V. Joshi, Tanay Karnik, Mehran Mozaffari Kermani, Chulwoo Kim, Tae-Hyoung Kim, Jaydeep P. Kulkarni, Eren Kursun, Erik Larsson, Hai (Helen) Li, Huawei Li, Patrick P. Mercier, Prabhat Mishra, Makoto Nagata, Arun S. Natarajan, Koji Nii, Partha Pratim Pande, Ioannis Savidis, Mingoo Seok, Sheldon X.-D. Tan, Mark Tehranipoor, Aida Todri-Sanial, Miroslav N. Velev, Xiaoqing Wen, Jiang Xu, Wei Zhang, Zhengya Zhang, Stacey Weber Jackson
2017	J	`jnl`	Hybrid Hardware/Software Floating-Point Implementations for Optimized Area and Throughput Tradeoffs. IEEE Trans. Very Large Scale Integr. Syst. Jon J. Pimentel, Brent Bohnenstiehl, Bevan M. Baas
2017	J	`jnl`	KiloCore: A 32-nm 1000-Processor Computational Array. IEEE J. Solid State Circuits Brent Bohnenstiehl, Aaron Stillmaker, Jon J. Pimentel, Timothy Andreas, Bin Liu, Anh Tran, Emmanuel Adeagbo, Bevan M. Baas
2017	J	`jnl`	KiloCore: A Fine-Grained 1, 000-Processor Array for Task-Parallel Applications. IEEE Micro Brent Bohnenstiehl, Aaron Stillmaker, Jon J. Pimentel, Timothy Andreas, Bin Liu, Anh Tran, Emmanuel Adeagbo, Bevan M. Baas
2017	J	`jnl`	Scaling equations for the accurate prediction of CMOS device performance from 180 nm to 7 nm. Integr. Aaron Stillmaker, Bevan M. Baas
2016	—	`conf`	A 5.8 pJ/Op 115 billion ops/sec, to 1.78 trillion ops/sec 32nm 1000-processor array. VLSI Circuits Brent Bohnenstiehl, Aaron Stillmaker, Jon J. Pimentel, Timothy Andreas, Bin Liu, Anh Tran, Emmanuel Adeagbo, Bevan M. Baas
2016	—	`conf`	KiloCore: A 32 nm 1000-processor array. Hot Chips Symposium Brent Bohnenstiehl, Aaron Stillmaker, Jon J. Pimentel, Timothy Andreas, Bin Liu, Anh Tran, Emmanuel Adeagbo, Bevan M. Baas
2015	Misc	`conf`	A software LDPC decoder implemented on a many-core array of programmable processors. ACSSC Brent Bohnenstiehl, Bevan M. Baas
2015	Misc	`conf`	Area efficient backprojection computation with reduced floating-point word width for SAR image formation. ACSSC Jon J. Pimentel, Aaron Stillmaker, Brent Bohnenstiehl, Bevan M. Baas
2015	—	`conf`	Optimizing power of many-core systems by exploiting dynamic voltage, frequency and core scaling. MWSCAS Bin Liu, Mohammad H. Foroozannejad, Soheil Ghiasi, Bevan M. Baas
2014	J	`jnl`	Achieving High-Performance On-Chip Networks With Shared-Buffer Routers. IEEE Trans. Very Large Scale Integr. Syst. Anh Thien Tran, Bevan M. Baas
2014	Misc	`conf`	Hybrid floating-point modules with low area overhead on a fine-grained processing core. ACSSC Jon J. Pimentel, Bevan M. Baas
2014	J	`jnl`	Processor Tile Shapes and Interconnect Topologies for Dense On-Chip Networks. IEEE Trans. Very Large Scale Integr. Syst. Zhibin Xiao, Bevan M. Baas
2014	Misc	`conf`	Scalable hardware-based power management for many-core systems. ACSSC Bin Liu, Brent Bohnenstiehl, Bevan M. Baas
2014	J	`jnl`	Time-Scalable Mapping for Circuit-Switched GALS Chip Multiprocessor Platforms. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Mohammad H. Foroozannejad, Matin Hashemi, Alireza Mahini, Bevan M. Baas, Soheil Ghiasi
2013	J	`jnl`	LDPC Decoder with an Adaptive Wordwidth Datapath for Energy and BER Co-Optimization. VLSI Design Tinoosh Mohsenin, Houshmand Shirani-mehr, Bevan M. Baas
2013	J	`jnl`	Parallel AES Encryption Engines for Many-Core Processor Arrays. IEEE Trans. Computers Bin Liu, Bevan M. Baas
2012	—	`conf`	A Hexagonal Processor and Interconnect Topology for Many-Core Architecture with Dense On-Chip Networks. VLSI-SoC (Selected Papers) Zhibin Xiao, Bevan M. Baas
2012	C	`conf`	A hexagonal shaped processor and interconnect topology for tightly-tiled many-core architecture. VLSI-SoC Zhibin Xiao, Bevan M. Baas
2012	B	`conf`	Fine-Grained Energy-Efficient Sorting on a Many-Core Processor Array. ICPADS Aaron Stillmaker, Lucas Stillmaker, Bevan M. Baas
2011	J	`jnl`	A 1080p H.264/AVC Baseline Residual Encoder for a Fine-Grained Many-Core System. IEEE Trans. Circuits Syst. Video Technol. Zhibin Xiao, Bevan M. Baas
2011	—	`conf`	A fine-grained parallel implementation of a H.264/AVC encoder on a 167-processor computational platform. ACSCC Zhibin Xiao, Stephen Le, Bevan M. Baas
2011	—	`conf`	A high-performance area-efficient AES cipher on a many-core platform. ACSCC Bin Liu, Bevan M. Baas
2011	—	`conf`	A reduced routing network architecture for partial parallel LDPC decoders. ACSCC Houshmand Shirani-mehr, Tinoosh Mohsenin, Bevan M. Baas
2011	C	`conf`	Low power LDPC decoder with efficient stopping scheme for undecodable blocks. ISCAS Tinoosh Mohsenin, Houshmand Shirani-mehr, Bevan M. Baas
2011	C	`conf`	RoShaQ: High-performance on-chip router with shared queues. ICCD Anh Thien Tran, Bevan M. Baas
2010	J	`jnl`	A Low-Area Multi-Link Interconnect Architecture for GALS Chip Multiprocessors. IEEE Trans. Very Large Scale Integr. Syst. Zhiyi Yu, Bevan M. Baas
2010	J	`jnl`	A Low-Complexity Message-Passing Algorithm for Reduced Routing Congestion in LDPC Decoders. IEEE Trans. Circuits Syst. I Regul. Pap. Tinoosh Mohsenin, Dean Nguyen Truong, Bevan M. Baas
2010	J	`jnl`	A Reconfigurable Source-Synchronous On-Chip Network for GALS Many-Core Platforms. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Anh Thien Tran, Dean Nguyen Truong, Bevan M. Baas
2010	J	`jnl`	A Split-Decoding Message Passing Algorithm for Low Density Parity Check Decoders. J. Signal Process. Syst. Tinoosh Mohsenin, Bevan M. Baas
2010	A*	`conf`	Circuit modeling for practical many-core architecture design exploration. DAC Dean Truong, Bevan M. Baas
2009	J	`jnl`	A 167-Processor Computational Platform in 65 nm CMOS. IEEE J. Solid State Circuits Dean Nguyen Truong, Wayne H. Cheng, Tinoosh Mohsenin, Zhiyi Yu, Anthony T. Jacobson, Gouri Landge, Michael J. Meeuwsen, Christine Watnik, Anh Thien Tran, Zhibin Xiao, Eric W. Work, Jeremy W. Webb, Paul Vincent Mejia, Bevan M. Baas
2009	—	`conf`	A GALS many-core heterogeneous DSP platform with source-synchronous on-chip interconnection network. NOCS Anh Thien Tran, Dean Truong, Bevan M. Baas
2009	C	`conf`	A Low-cost High-speed Source-synchronous Interconnection Technique for GALS Chip Multiprocessors. ISCAS Anh Thien Tran, Dean Nguyen Truong, Bevan M. Baas
2009	—	`conf`	An Improved Split-Row Threshold Decoding Algorithm for LDPC Codes. ICC Tinoosh Mohsenin, Dean Truong, Bevan M. Baas
2009	J	`jnl`	High Performance, Energy Efficiency, and Scalability With GALS Chip Multiprocessors. IEEE Trans. Very Large Scale Integr. Syst. Zhiyi Yu, Bevan M. Baas
2009	C	`conf`	Multi-Split-Row Threshold Decoding Implementations for LDPC Codes. ISCAS Tinoosh Mohsenin, Dean Nguyen Truong, Bevan M. Baas
2009	C	`conf`	The Design of a Reconfigurable Continuous-flow Mixed-radix FFT Processor. ISCAS Anthony T. Jacobson, Dean Nguyen Truong, Bevan M. Baas
2008	—	`conf`	A complete real-time 802.11a baseband receiver implemented on an array of programmable processors. ACSCC Anh Thien Tran, Dean Nguyen Truong, Bevan M. Baas
2008	C	`conf`	A high-performance parallel CAVLC encoder on a fine-grained many-core system. ICCD Zhibin Xiao, Bevan M. Baas
2008	C	`conf`	A low-area interconnect architecture for chip multiprocessors. ISCAS Zhiyi Yu, Bevan M. Baas
2008	—	`conf`	A thresholding algorithm for improved Split-Row decoding of LDPC codes. ACSCC Tinoosh Mohsenin, Pascal Urard, Bevan M. Baas
2008	J	`jnl`	Architecture and Evaluation of an Asynchronous Array of Simple Processors. J. Signal Process. Syst. Zhiyi Yu, Michael J. Meeuwsen, Ryan W. Apperson, Omar Sattari, Michael A. Lai, Jeremy W. Webb, Eric W. Work, Tinoosh Mohsenin, Bevan M. Baas
2008	J	`jnl`	AsAP: An Asynchronous Array of Simple Processors. IEEE J. Solid State Circuits Zhiyi Yu, Michael J. Meeuwsen, Ryan W. Apperson, Omar Sattari, Michael A. Lai, Jeremy W. Webb, Eric W. Work, Dean Truong, Tinoosh Mohsenin, Bevan M. Baas
2008	C	`conf`	Dynamic voltage and frequency scaling circuits with two supply voltages. ISCAS Wayne H. Cheng, Bevan M. Baas
2007	J	`jnl`	A Scalable Dual-Clock FIFO for Data Transfers Between Arbitrary and Haltable Clock Domains. IEEE Trans. Very Large Scale Integr. Syst. Ryan W. Apperson, Zhiyi Yu, Michael J. Meeuwsen, Tinoosh Mohsenin, Bevan M. Baas
2007	J	`jnl`	A Shared Memory Module for Asynchronous Arrays of Processors. EURASIP J. Embed. Syst. Michael J. Meeuwsen, Zhiyi Yu, Bevan M. Baas
2007	J	`jnl`	AsAP: A Fine-Grained Many-Core Platform for DSP Applications. IEEE Micro Bevan M. Baas, Zhiyi Yu, Michael J. Meeuwsen, Omar Sattari, Ryan W. Apperson, Eric W. Work, Jeremy W. Webb, Michael A. Lai, Tinoosh Mohsenin, Dean Truong, Jason Cheung
2007	—	`conf`	High-Throughput LDPC Decoders Using A Multiple Split-Row Method. ICASSP (2) Tinoosh Mohsenin, Bevan M. Baas
2006	—	`conf`	An asynchronous array of simple processors for dsp applications. ISSCC Zhiyi Yu, Michael J. Meeuwsen, Ryan W. Apperson, Omar Sattari, Michael A. Lai, Jeremy W. Webb, Eric W. Work, Tinoosh Mohsenin, Mandeep Singh, Bevan M. Baas
2006	—	`conf`	Hardware and applications of AsAP: An asynchronous array of simple processors. Hot Chips Symposium Bevan M. Baas, Zhiyi Yu, Michael J. Meeuwsen, Omar Sattari, Ryan W. Apperson, Eric W. Work, Jeremy W. Webb, Michael A. Lai, Daniel Gurman, Chi Chen, Jason Cheung, Dean Truong, Tinoosh Mohsenin
2006	C	`conf`	Implementing Tile-based Chip Multiprocessors with GALS Clocking Styles. ICCD Zhiyi Yu, Bevan M. Baas
2006	—	`conf`	Performance and Power Analysis of Globally Asynchronous Locally Synchronous Multi-Processor Systems. ISVLSI Zhiyi Yu, Bevan M. Baas
2006	C	`conf`	Split-Row: A Reduced Complexity, High Throughput LDPC Decoder Architecture. ICCD Tinoosh Mohsenin, Bevan M. Baas
2005	—	`conf`	A generalized cached-FFT algorithm. ICASSP (5) Bevan M. Baas
1999	J	`jnl`	A low-power, high-performance, 1024-point FFT processor. IEEE J. Solid State Circuits Bevan M. Baas
1998	—	`conf`	A 9.5 mW 330 μsec 1024-point FFT processor. CICC Bevan M. Baas