Bernhard Wicht

55 papers C 5Journal 14Unranked 36

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	3.3 A Passive Switched-Capacitor-Based Multimode Amplifier with a Logarithmic Conformity Error of 0.75 ISSCC Hendrik Siemssen, Rochus Nowosielski, Holger Borchardt, Jan Mueller, Bernhard Wicht
2025	—	`conf`	A Low-Distortion Adderless Zero-Time Reset Incremental Delta-Sigma Analog-to-Digital Converter. PRIME Jesko Flemming, Kaxin Tang, Bernhard Wicht, Pascal Witte
2025	—	`conf`	A Spur-Reduced Power-Efficient Fully Differential VCO-based Operational Transconductance Amplifier. PRIME Kaxin Tang, Jesko Flemming, Hendrik Siemssen, Pascal Witte, Bernhard Wicht
2025	J	`jnl`	A Trimming-Free 3-in-1 Multi-Mode Passive Switched-Capacitor Amplifier With an Absolute Logarithmic Error of 0.5 dB up to 200 IEEE J. Solid State Circuits Hendrik Siemssen, Rochus Nowosielski, Holger Borchardt, Jan Mueller, Bernhard Wicht
2025	—	`conf`	HOOP: A Scalable Hybrid DC-DC Converter Ring for High-Performance Computing. ISSCC Zhiguo Tong, Zhewen Yu, Junwei Huang, Xiangyu Mao, Bernhard Wicht, Rui Paulo Martins, Yan Lu
2024	—	`conf`	31.10 A Fully integrated 500V, 6.25MHz GaN-IC for Totem-Pole PFC Off-Line Power Conversion. ISSCC Niklas Deneke, Bernhard Wicht
2024	C	`conf`	A DAC Sharing and Linearization Technique for Time-Interleaved Incremental Delta-Sigma ADCs. ISCAS Jesko Flemming, Bernhard Wicht, Pascal Witte
2024	J	`jnl`	A Dual-Inductor Ladder Buck Converter for Li-Ion Battery-Operated Sub-Volt SoCs. IEEE J. Solid State Circuits Arindam Mishra, Wei Zhu, Bernhard Wicht, Valentijn De Smedt
2024	—	`conf`	A Hardware Efficient Digital DAC Linearization Topology for Delta-Sigma ADCs. SMACD Jesko Flemming, Timon Rogge, Bernhard Wicht, Pascal Witte
2023	—	`conf`	A 2-8V Vin 670mA Scalable Multi-Ratio SC DCDC Converter for MCU Integration in 28nm CMOS Achieving 91% Peak Efficiency. ESSCIRC Adrian Gehl, Kyrylo Cherniak, Olga Kharko, Gianluca Marin, Petru Bacinski, Frank Prämaßing, Bernhard Wicht
2023	C	`conf`	A Noise-Canceling SMASH Architecture for Discrete-Time Bandpass Delta-Sigma ADCs. ISCAS Jesko Flemming, Bernhard Wicht, Pascal Witte
2023	—	`conf`	Stability Analysis for Frequency Tunable Bandpass Delta-Sigma ADC Architectures. SMACD Jesko Flemming, Bernhard Wicht, Pascal Witte
2022	J	`jnl`	A 110/230 V AC and 15-400 V DC 0.3 W Power-Supply IC With Integrated Active Zero-Crossing Buffer. IEEE J. Solid State Circuits Christoph Rindfleisch, Bernhard Wicht
2022	—	`conf`	A 110V/230V 0.3W Offline Chip-Scale Power Supply with Integrated Active Zero-Crossing Buffer and Voltage-Interval-Based Dual-Mode Control. ISSCC Christoph Rindfleisch, Bernhard Wicht
2022	—	`conf`	A Highly-Integrated 20-300V 0.5W Active-Clamp Flyback DCDC Converter with 76.7% Peak Efficiency. CICC Christoph Rindfleisch, Jens Otten, Bernhard Wicht
2021	J	`jnl`	A Resonant One-Step 325 V to 3.3-10 V DC-DC Converter With Integrated Power Stage Benefiting From High-Voltage Loss-Reduction Techniques. IEEE J. Solid State Circuits Christoph Rindfleisch, Bernhard Wicht
2021	—	`conf`	Session 33 Overview: High-Voltage, GaN and Wireless Power Power Management Subcommittee. ISSCC Min Chen, Bernhard Wicht, Kousuke Miyaji
2020	—	`conf`	11.3 A One-Step 325V to 3.3-to-10V 0.5W Resonant DC-DC Converter with Fully Integrated Power Stage and 80.7% Efficiency. ISSCC Christoph Rindfleisch, Bernhard Wicht
2020	—	`conf`	18.2 A Monolithic E-Mode GaN 15W 400V Offline Self-Supplied Hysteretic Buck Converter with 95.6% Efficiency. ISSCC Maik Kaufmann, Michael Lueders, Cetin Kaya, Bernhard Wicht
2020	J	`jnl`	A Monolithic GaN-IC With Integrated Control Loop for 400-V Offline Buck Operation Achieving 95.6% Peak Efficiency. IEEE J. Solid State Circuits Maik Kaufmann, Bernhard Wicht
2020	—	`conf`	Long, Short, Monolithic - The Gate Loop Challenge for GaN Drivers: Invited Paper. CICC Maik Kaufmann, Achim Seidel, Bernhard Wicht
2019	—	`conf`	A 30 ns 16 Mb 2 b/cell Embedded Flash with Ramped Gate Time-Domain Sensing Scheme for Automotive Application. VLSI-DAT Sebastian Kiesel, Thomas Kern, Bernhard Wicht, Helmut Graeb
2019	—	`conf`	A Fully Integrated 85%-Peak-Efficiency Hybrid Multi Ratio Resonant DC-DC Converter with 3.0-to-4.5V Input and 500μA -to-120mA Load Range. ISSCC Peter Renz, Maik Kaufmann, Michael Lueders, Bernhard Wicht
2019	J	`jnl`	Introduction to the Special Issue on the 2019 IEEE International Solid-State Circuits Conference (ISSCC). IEEE J. Solid State Circuits Youngcheol Chae, Bernhard Wicht, Bob Verbruggen, Payam Heydari, Howard C. Luong
2018	J	`jnl`	A 48-V Wide-V IEEE J. Solid State Circuits Juergen Wittmann, Tobias Funk, Thoralf Rosahl, Bernhard Wicht
2018	—	`conf`	A 50V, 1.45ns, 4.1pJ High-Speed Low-Power Level Shifter for High-Voltage DCDC Converters. ESSCIRC Daniel Lutz, Achim Seidel, Bernhard Wicht
2018	—	`conf`	A Boost Converter with 3-6V Input and Fast Transient Digital Control Comprising a 90 ns-Latency Live-Tracking Window ADC. ESSCIRC Samuel Quenzer-Hohmuth, Steffen Ritzmann, Thoralf Rosahl, Bernhard Wicht
2018	J	`jnl`	A Hysteretic Buck Converter With 92.1% Maximum Efficiency Designed for Ultra-Low Power and Fast Wake-Up SoC Applications. IEEE J. Solid State Circuits Francesco Santoro, Rüdiger Kuhn, Neil Gibson, Nicola Rasera, Thomas Tost, Helmut Graeb, Bernhard Wicht, Ralf Brederlow
2018	—	`conf`	A fully integrated DC to 75 MHz current sensing circuit with on-chip Rogowski coil. CICC Tobias Funk, Bernhard Wicht
2018	—	`conf`	A fully integrated three-level 11.6nC gate driver supporting GaN gate injection transistors. ISSCC Achim Seidel, Bernhard Wicht
2018	—	`conf`	F6: Advances in energy efficient analog design. ISSCC Axel Thomsen, Bernhard Wicht, Pieter Harpe, Man Kay Law, Young Cheol Chae
2018	J	`jnl`	Integrated Gate Drivers Based on High-Voltage Energy Storing for GaN Transistors. IEEE J. Solid State Circuits Achim Seidel, Bernhard Wicht
2017	—	`conf`	25.3 A 1.3A gate driver for GaN with fully integrated gate charge buffer capacitor delivering 11nC enabled by high-voltage energy storing. ISSCC Achim Seidel, Bernhard Wicht
2017	—	`conf`	A 12-48 V wide-vin 9-15 MHz soft-switching controlled resonant DCDC converter. ESSCIRC Juergen Wittmann, Tobias Funk, Thoralf Rosahl, Bernhard Wicht
2017	—	`conf`	Time-domain ramped gate sensing for embedded multi-level flash in automotive applications. MWSCAS Sebastian Kiesel, Thomas Kern, Bernhard Wicht
2016	—	`conf`	12.4 A 10mW fully integrated 2-to-13V-input buck-boost SC converter with 81.5% peak efficiency. ISSCC Daniel Lutz, Peter Renz, Bernhard Wicht
2016	—	`conf`	A 120/230 Vrms-to-3.3V micro power supply with a fully integrated 17V SC DCDC converter. ESSCIRC Daniel Lutz, Peter Renz, Bernhard Wicht
2016	—	`conf`	A 40V current sensing circuit with fast on/off transition for high-voltage power management. MWSCAS Peter Renz, Philipp Lamprecht, Daniel Teufel, Bernhard Wicht
2016	J	`jnl`	An 18 V Input 10 MHz Buck Converter With 125 ps Mixed-Signal Dead Time Control. IEEE J. Solid State Circuits Juergen Wittmann, Alexander Barner, Thoralf Rosahl, Bernhard Wicht
2016	—	`conf`	Gate driver with 10 / 15ns in-transition variable drive current and 60% reduced current dip. ESSCIRC Alexis Schindler, Benno Koeppl, Ansgar Pottbaecker, Markus Zannoth, Bernhard Wicht
2015	—	`conf`	A 12V 10MHz buck converter with dead time control based on a 125 ps differential delay chain. ESSCIRC Juergen Wittmann, Alexander Barner, Thoralf Rosahl, Bernhard Wicht
2015	C	`conf`	A 20 V, 8 MHz resonant DCDC converter with predictive control for 1 ns resolution soft-switching. ISCAS Tobias Funk, Juergen Wittmann, Thoralf Rosahl, Bernhard Wicht
2015	J	`jnl`	Area Efficient Integrated Gate Drivers Based on High-Voltage Charge Storing. IEEE J. Solid State Circuits Achim Seidel, Marco Salvatore Costa, Joachim Joos, Bernhard Wicht
2015	—	`conf`	EMC and switching loss improvement for fast switching power stages by di/dt, dv/dt optimization with 10ns variable current source gate driver. EMC Compo Alexis Schindler, Benno Koeppl, Bernhard Wicht
2014	—	`conf`	A 50V high-speed level shifter with high dv/dt immunity for multi-MHz DCDC converters. ESSCIRC Juergen Wittmann, Thoralf Rosahl, Bernhard Wicht
2014	—	`conf`	Bootstrap circuit with high-voltage charge storing for area efficient gate drivers in power management systems. ESSCIRC Achim Seidel, Marco Salvatore Costa, Joachim Joos, Bernhard Wicht
2013	C	`conf`	Authentic mode-toggled detector with fast transient response under wide load range buck-boost converter. ISCAS Moris Lin, Yung-Sheng Huang, Andreas Ehrhart, Yu-Huei Lee, Chao-Chang Chiu, Bernhard Wicht, Ke-Horng Chen
2013	—	`conf`	EMC analysis of current source gate drivers. EMC Compo Alexis Schindler, Benno Koeppl, Bernhard Wicht
2011	C	`conf`	EMC influence of the charge pump in linear regulators - Design, simulation and measurements. ISCAS Juergen Wittmann, Bernhard Wicht
2009	—	`conf`	Capacitive-coupled current sensing and Auto-ranging slope compensation for current mode SMPS with wide supply and frequency range. ESSCIRC Stefan Herzer, Sumeet Kulkarni, Maciej Jankowski, Jochen Neidhardt, Bernhard Wicht
2008	J	`jnl`	A Configurable High-Side/Low-Side Driver With Fast and Equalized Switching Delay. IEEE J. Solid State Circuits Michael Wendt, Lenz Thoma, Bernhard Wicht, Doris Schmitt-Landsiedel
2007	—	`conf`	A configurable High-Side/ low-Side Driver. ESSCIRC Michael Wendt, Lenz Thoma, Bernhard Wicht, Doris Schmitt-Landsiedel
2004	J	`jnl`	Yield and speed optimization of a latch-type voltage sense amplifier. IEEE J. Solid State Circuits Bernhard Wicht, Thomas Nirschl, Doris Schmitt-Landsiedel
2003	—	`conf`	A yield-optimized latch-type SRAM sense amplifier. ESSCIRC Bernhard Wicht, Thomas Nirschl, Doris Schmitt-Landsiedel
2001	J	`jnl`	Analysis and compensation of the bitline multiplexer in SRAM current sense amplifiers. IEEE J. Solid State Circuits Bernhard Wicht, Steffen Paul, Doris Schmitt-Landsiedel