Bernhard Hoppe

12 papers A* 1B 1C 2Journal 3Unranked 5
YearRankTypeTitle / Venue / Authors
2012 J jnl
Opening a M. Sc. in Electrical Engineering for non-traditional Students.
Int. J. Adv. Corp. Learn.
Anja Lina Müller, Andreas Schwarzbacher, Bernhard Hoppe
2012 C conf
Opening a M. Sc. in electrical engineering for non-traditional students.
EDUCON
Anja Lina Müller, Bernhard Hoppe, Andreas Schwarzbacher
2007 C conf
A FPGA Optimised Digital Real-Time Mutichannel Correlator Architecture.
DSD
Christian Jakob, A. Th. Schwarzbacher, Bernhard Hoppe, Reiner Peters
2007 — conf
A Multichannel Digital Real-Time Correlator as Single FPGA Implementation.
DSP
Christian Jakob, A. Th. Schwarzbacher, Bernhard Hoppe, Reiner Peters
2004 B conf
FPGA-Efficient Hybrid LUT/CORDIC Architecture.
FPL
Ireneusz Janiszewski, Hermann Meuth, Bernhard Hoppe
2004 — conf
FPGA-efficient phase-to-I/Q architecture.
SoCC
Ireneusz Janiszewski, Hermann Meuth, Bernhard Hoppe
2002 — conf
Modelling and Simulation in the Design Flow for Numerically Controlled Oscillators.
ESM
Ireneusz Janiszewski, Bernhard Hoppe, Hermann Meuth
2001 A* conf
VHDL-Based Design and Design Methodology for Reusable High Performance Direct Digital Frequency Synthesizers.
DAC
Ireneusz Janiszewski, Bernhard Hoppe, Hermann Meuth
1999 — conf
A single chip 200 MHz digital correlation system for laser spectroscopy with 512 correlation channels.
ISCAS (5)
Martin Engels, Bernhard Hoppe, Hermann Meuth, Reiner Peters
1990 J jnl
Optimization of high-speed CMOS logic circuits with analytical models for signal delay, chip area, and dynamic power dissipation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Bernhard Hoppe, Gerd Neuendorf, Doris Schmitt-Landsiedel, J. Will Specks
1990 J jnl
Pipelined architecture for fast CMOS buffer RAMs.
IEEE J. Solid State Circuits
Doris Schmitt-Landsiedel, Bernhard Hoppe, Gerd Neuendorf, Maria Wurm, Josef Winnerl
1990 — conf
Transmission gate delay models for circuit optimization.
EURO-DAC
Veronika Eisele, Bernhard Hoppe, Oliver Kiehl