Beomsup Kim - RankMe

41 papers C 4Misc 1Journal 26Unranked 10

Year	Rank	Type	Title / Venue / Authors
2017	J	`jnl`	A 48-MHz Differential Crystal Oscillator With 168-fs Jitter in 28-nm CMOS. IEEE J. Solid State Circuits Yashar Rajavi, Mohammad Mahdi Ghahramani, Alireza Khalili, Amirpouya Kavousian, Beomsup Kim, Michael P. Flynn
2012	J	`jnl`	Low-Voltage Low-Power 1.6 GHz Quadrature Signal Generation Through Stacking a Transformer-Based VCO and a Divide-by-Two. IEEE Trans. Circuits Syst. I Regul. Pap. Shen Wang, Vipul Chawla, Dong Sam Ha, Beomsup Kim
2011	—	`conf`	A combined VCO and divide-by-two for low-voltage low-power 1.6 GHz quadrature signal generation. CICC Shen Wang, Dong Sam Ha, Beomsup Kim, Vipul Chawla
2005	J	`jnl`	A DLL-Based Frequency Synthesizer with Selective Reuse of a Delay Cell Scheme for 2.4 GHz ISM Band. IEICE Trans. Electron. Seok Kang, Beomsup Kim
2005	J	`jnl`	A four-channel 3.125-Gb/s/ch CMOS serial-link transceiver with a mixed-mode adaptive equalizer. IEEE J. Solid State Circuits Jinwook Kim, Jeongsik Yang, Sangjin Byun, Hyunduk Jun, Jeongkyu Park, Cormac S. G. Conroy, Beomsup Kim
2005	J	`jnl`	A third-order ΣΔ modulator in 0.18-μm CMOS with calibrated mixed-mode integrators. IEEE J. Solid State Circuits Jae Hoon Shim, In-Cheol Park, Beomsup Kim
2005	J	`jnl`	An Efficient Software-Defined Radio Architecture for Multi-Mode WCDMA Applications. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Jaesang Lim, Yongchul Song, Jeong Pyo Kim, Beomsup Kim
2005	J	`jnl`	Analysis and Design of Multistage Low-Phase-Noise CMOS LC-Ring Oscillators. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Jaesang Lim, Jaejoon Kim, Beomsup Kim
2005	J	`jnl`	Correction to "A Third-Order$Sigma Delta $Modulator in 0.18-$muhboxm$CMOS With Calibrated Mixed-Mode Integrators". IEEE J. Solid State Circuits Jae Hoon Shim, In-Cheol Park, Beomsup Kim
2005	J	`jnl`	Hybrid ΣΔ modulators with adaptive calibration. IEEE Trans. Circuits Syst. I Regul. Pap. Jae Hoon Shim, In-Cheol Park, Beomsup Kim
2004	J	`jnl`	A 14-b direct digital frequency synthesizer with sigma-delta noise shaping. IEEE J. Solid State Circuits Yongchul Song, Beomsup Kim
2004	J	`jnl`	A quadrature digital synthesizer/mixer architecture using fine/coarse coordinate rotation to achieve 14-b input, 15-b output, and 100-dBc SFDR. IEEE J. Solid State Circuits Yongchul Song, Beomsup Kim
2004	J	`jnl`	Quadrature direct digital frequency synthesizers using interpolation-based angle rotation. IEEE Trans. Very Large Scale Integr. Syst. Yongchul Song, Beomsup Kim
2003	—	`conf`	A 330-MHz 15-b quadrature digital synthesizer/mixer in 0.25-μm CMOS. ESSCIRC Yongchul Song, Beomsup Kim
2003	—	`conf`	A 5-GHz self-calibrated I/Q clock generator using a quadrature LC-VCO. ISCAS (1) Hyung Ki Ahn, In-Cheol Park, Beomsup Kim
2003	—	`conf`	A hybrid delta-sigma modulator with adaptive calibration. ISCAS (1) Jae Hoon Shim, In-Cheol Park, Beomsup Kim
2003	J	`jnl`	A low-power CMOS Bluetooth RF transceiver with a digital offset canceling DLL-based GFSK demodulator. IEEE J. Solid State Circuits Sangjin Byun, Chan-Hong Park, Yongchul Song, Sung-Ho Wang, Cormac S. G. Conroy, Beomsup Kim
2003	J	`jnl`	Low-jitter digital timing recovery techniques for CAP-based VDSL applications. IEEE J. Solid State Circuits Yongchul Song, Beomsup Kim
2001	J	`jnl`	A 1.8-GHz self-calibrated phase-locked loop with precise I/Q matching. IEEE J. Solid State Circuits Chan-Hong Park, Ook Kim, Beomsup Kim
2001	J	`jnl`	A 500-Mb/s quadruple data rate SDRAM interface using a skew cancellation technique. IEEE J. Solid State Circuits Sung-Ho Wang, Jeongpyo Kim, Joonsuk Lee, Hyoung Sik Nam, Young Gon Kim, Jae Hoon Shim, Hyung Ki Ahn, Seok Kang, Bong Hwa Jeong, Jin-Hong Ahn, Beomsup Kim
2001	Misc	`conf`	Digital timing synchronization with jitter reduction technique for cap-based VDSL system. ICASSP Yongchul Song, Kyehyung Lee, Beomsup Kim
2000	J	`jnl`	A low-jitter mixed-mode DLL for high-speed DRAM applications. IEEE J. Solid State Circuits Jae Joon Kim, Sang-Bo Lee, Tae-Sung Jung, Chang-Hyun Kim, Soo-In Cho, Beomsup Kim
2000	J	`jnl`	A low-noise fast-lock phase-locked loop with adaptive bandwidth control. IEEE J. Solid State Circuits Joonsuk Lee, Beomsup Kim
2000	J	`jnl`	A low-noise phase-locked loop design by loop bandwidth optimization. IEEE J. Solid State Circuits Kyoohyun Lim, Chan-Hong Park, Dal-Soo Kim, Beomsup Kim
2000	—	`conf`	Non-Data-Aided Timing Recovery Algorithm for \pi/4-OPSK Modulated Signals. ICC (1) Beomsup Kim, Joonsuk Lee, Seung Hee Choi, Jun Mo Koo, Byung Jun Min
1999	—	`conf`	16-bit DSP and System for Baseband / Voiceband Processing of IS-136 Cellular Telephony. ASP-DAC Tae Hun Kim, Jeongsik Yang, Kyoo Hyun Lim, Jin Wook Kim, Jeong Eun Lee, Hyoung Sik Nam, Young Gon Kim, Jeong Pyo Kim, Sangjin Byun, Bae Sung Kwon, Beomsup Kim
1999	J	`jnl`	A low-noise, 900-MHz VCO in 0.6-μm CMOS. IEEE J. Solid State Circuits Chan-Hong Park, Beomsup Kim
1998	J	`jnl`	A 64-Mbit, 640-MByte/s bidirectional data strobed, double-data-rate SDRAM with a 40-mW DLL for a 256-MByte memory system. IEEE J. Solid State Circuits Chang-Hyun Kim, Jung-Hwa Lee, J. B. Lee, Beomsup Kim, C. S. Park, Sang-Bo Lee, S. Y. Lee, C. W. Park, J. G. Roh, Hyoung Sik Nam, D. Y. Kim, D. Y. Lee, Tae-Sung Jung, Hongil Yoon, Soo-In Cho
1998	—	`conf`	Dual-loop Digital PLL Design for Adaptive Clock Recovery. ASP-DAC Tae Hun Kim, Beomsup Kim
1997	—	`conf`	A Digital Phase-Locked Loop with Variable Loop Gains Derived from RLS Method. ICC (1) Byungjin Chun, Seung Hee Choi, Beomsup Kim
1997	J	`jnl`	A fully integrated low-noise 1-GHz frequency synthesizer design for mobile communication application. IEEE J. Solid State Circuits Seog-Jun Lee, Beomsup Kim, Kwyro Lee
1997	J	`jnl`	A novel high-speed ring oscillator for multiphase clock generation using negative skewed delay scheme. IEEE J. Solid State Circuits Seog-Jun Lee, Beomsup Kim, Kwyro Lee
1997	J	`jnl`	Design of variable loop gains of dual-loop DPLL. IEEE Trans. Commun. Byungjin Chun, Yong Hoon Lee, Beomsup Kim
1997	—	`conf`	Optimal loop bandwidth design for low noise PLL applications. ASP-DAC Kyoohyun Lim, Seung Hee Choi, Beomsup Kim
1995	—	`conf`	A digital audio signal processor for cellular phone application. ASP-DAC Jeongsik Yang, Chanhong Park, Beomsup Kim
1995	C	`conf`	Adaptive Carrier Recovery Using Multi-Order DPLL for Mobile Communication Applications. ISCAS Byungjin Chun, Beomsup Kim, Yong Hong Lee
1994	C	`conf`	Analysis of Timing Jitter in CMOS Ring Oscillators. ISCAS Todd C. Weigandt, Beomsup Kim, Paul R. Gray
1994	C	`conf`	PLL/DLL System Noise Analysis for Low Jitter Clock Synthesizer Design. ISCAS Beomsup Kim, Todd C. Weigandt, Paul R. Gray
1993	C	`conf`	Optical MMSE gear-shifting algorithm for the fast synchronization of DPLL. ISCAS Beomsup Kim
1991	J	`jnl`	A 13-b 2.5-MHz self-calibrated pipelined A/D converter in 3- mu m CMOS. IEEE J. Solid State Circuits Yuh-Min Lin, Beomsup Kim, Paul R. Gray
1990	J	`jnl`	A 30-MHz hybrid analog/digital clock recovery circuit in 2- mu m CMOS. IEEE J. Solid State Circuits Beomsup Kim, David N. Helman, Paul R. Gray