Benwei Xu

14 papers C 1Journal 7Unranked 6

Year	Rank	Type	Title / Venue / Authors
2019	J	`jnl`	A 12-b 1-GS/s 31.5-mW Time-Interleaved SAR ADC With Analog HPF-Assisted Skew Calibration and Randomly Sampling Reference ADC. IEEE J. Solid State Circuits Yuan Zhou, Benwei Xu, Yun Chiu
2019	J	`jnl`	A 78.5-dB SNDR Radiation- and Metastability-Tolerant Two-Step Split SAR ADC Operating Up to 75 MS/s With 24.9-mW Power Consumption in 65-nm CMOS. IEEE J. Solid State Circuits Hongda Xu, Hai Huang, Yongda Cai, Ling Du, Yuan Zhou, Benwei Xu, Datao Gong, Jingbo Ye, Yun Chiu
2017	—	`conf`	28.6 A 78.5dB-SNDR radiation- and metastability-tolerant two-step split SAR ADC operating up to 75MS/s with 24.9mW power consumption in 65nm CMOS. ISSCC Hongda Xu, Yongda Cai, Ling Du, Yuan Zhou, Benwei Xu, Datao Gong, Jingbo Ye, Yun Chiu
2017	J	`jnl`	A 23-mW 24-GS/s 6-bit Voltage-Time Hybrid Time-Interleaved ADC in 28-nm CMOS. IEEE J. Solid State Circuits Benwei Xu, Yuan Zhou, Yun Chiu
2017	—	`conf`	An 8b 1.39GS/S 0.85V two-step ADC with background comparator offset calibration. MWSCAS Sudipta Sarkar, Benwei Xu, Brian Elies, Yun Chiu
2016	—	`conf`	15.1 A 24.7mW 45MHz-BW 75.3dB-SNDR SAR-assisted CT ΔΣ modulator with 2nd-order noise coupling in 65nm CMOS. ISSCC Bo Wu, Shuang Zhu, Benwei Xu, Yun Chiu
2016	—	`conf`	A 23mW 24GS/s 6b Time-interleaved hybrid two-step ADC in 28nm CMOS. VLSI Circuits Benwei Xu, Yuan Zhou, Yun Chiu
2016	J	`jnl`	A 24.7 mW 65 nm CMOS SAR-Assisted CT ΔΣ Modulator With Second-Order Noise Coupling Achieving 45 MHz Bandwidth and 75.3 dB SNDR. IEEE J. Solid State Circuits Bo Wu, Shuang Zhu, Benwei Xu, Yun Chiu
2016	J	`jnl`	A Skew-Free 10 GS/s 6 bit CMOS ADC With Compact Time-Domain Signal Folding and Inherent DEM. IEEE J. Solid State Circuits Shuang Zhu, Benwei Xu, Bo Wu, Kiran Soppimath, Yun Chiu
2015	—	`conf`	A 0.073-mm CICC Shuang Zhu, Benwei Xu, Bo Wu, Kiran Soppimath, Yun Chiu
2015	J	`jnl`	A 12 bit 160 MS/s Two-Step SAR ADC With Background Bit-Weight Calibration Using a Time-Domain Proximity Detector. IEEE J. Solid State Circuits Yuan Zhou, Benwei Xu, Yun Chiu
2015	J	`jnl`	Comprehensive Background Calibration of Time-Interleaved Analog-to-Digital Converters. IEEE Trans. Circuits Syst. I Regul. Pap. Benwei Xu, Yun Chiu
2014	—	`conf`	A 12b 160MS/s synchronous two-step SAR ADC achieving 20.7fJ/step FoM with opportunistic digital background calibration. VLSIC Yuan Zhou, Benwei Xu, Yun Chiu
2013	C	`conf`	Background calibration of time-interleaved ADC using direct derivative information. ISCAS Benwei Xu, Yun Chiu