Benoît Tain - RankMe

12 papers A 2Journal 5Unranked 5

Year	Rank	Type	Title / Venue / Authors
2025	A	`conf`	J3DAI: A tiny DNN-Based Edge AI Accelerator for 3D-Stacked CMOS Image Sensor. ISLPED Benoît Tain, Raphael Millet, Romain Lemaire, Michal Szczepanski, Laurent Alacoque, Emmanuel Pluchart, Sylvain Choisnet, Rohit Prasad, Jérôme Chossat, Pascal Pierunek, Pascal Vivet, Sébastien Thuries
2025	J	`jnl`	J3DAI: A tiny DNN-Based Edge AI Accelerator for 3D-Stacked CMOS Image Sensor. CoRR Benoît Tain, Raphael Millet, Romain Lemaire, Michal Szczepanski, Laurent Alacoque, Emmanuel Pluchart, Sylvain Choisnet, Rohit Prasad, Jérôme Chossat, Pascal Pierunek, Pascal Vivet, Sébastien Thuries
2023	J	`jnl`	SamurAI: A Versatile IoT Node With Event-Driven Wake-Up and Embedded ML Acceleration. CoRR Ivan Miro-Panades, Benoît Tain, Jean-Frédéric Christmann, David Coriat, Romain Lemaire, Clement Jany, Baudouin Martineau, Fabrice Chaix, Guillaume Waltener, Emmanuel Pluchart, Jean-Philippe Noel, Adam Makosiej, Maxime Montoya, Simone Bacles-Min, David Briand, Jean-Marc Philippe, Yvain Thonnart, Alexandre Valentian, Frédéric Heitzmann, Fabien Clermidy
2023	J	`jnl`	SamurAI: A Versatile IoT Node With Event-Driven Wake-Up and Embedded ML Acceleration. IEEE J. Solid State Circuits Ivan Miro-Panades, Benoît Tain, Jean-Frédéric Christmann, David Coriat, Romain Lemaire, Clement Jany, Baudouin Martineau, Fabrice Chaix, Guillaume Waltener, Emmanuel Pluchart, Jean-Philippe Noel, Adam Makosiej, Maxime Montoya, Simone Bacles-Min, David Briand, Jean-Marc Philippe, Yvain Thonnart, Alexandre Valentian, Frédéric Heitzmann, Fabien Clermidy
2022	J	`jnl`	Generating Efficient FPGA-based CNN Accelerators from High-Level Descriptions. J. Signal Process. Syst. Nermine Ali, Jean-Marc Philippe, Benoît Tain, Philippe Coussy
2021	—	`conf`	Exploration and Generation of Efficient FPGA-based Deep Neural Network Accelerators. SiPS Nermine Ali, Jean-Marc Philippe, Benoît Tain, Philippe Coussy
2020	—	`conf`	Deep Neural Networks Characterization Framework for Efficient Implementation on Embedded Systems. SiPS Nermine Ali, Jean-Marc Philippe, Benoît Tain, Thomas Peyret, Philippe Coussy
2020	—	`conf`	SamurAI: A 1.7MOPS-36GOPS Adaptive Versatile IoT Node with 15, 000× Peak-to-Idle Power Reduction, 207ns Wake-Up Time and 1.3TOPS/W ML Efficiency. VLSI Circuits Ivan Miro Panades, Benoît Tain, Jean-Frédéric Christmann, David Coriat, Romain Lemaire, Clement Jany, Baudouin Martineau, Fabrice Chaix, Anthony Quelen, Emmanuel Pluchart, Jean-Philippe Noel, Reda Boumchedda, Adam Makosiej, Maxime Montoya, Simone Bacles-Min, David Briand, Jean-Marc Philippe, Alexandre Valentian, Frédéric Heitzmann, Edith Beigné, Fabien Clermidy
2018	A	`conf`	PNeuro: A scalable energy-efficient programmable hardware accelerator for neural networks. DATE Alexandre Carbon, Jean-Marc Philippe, Olivier Bichler, Renaud Schmit, Benoît Tain, David Briand, Nicolas Ventroux, Michel Paindavoine, Olivier Brousse
2014	J	`jnl`	A Fine-Grain Variation-Aware Dynamic Vdd-Hopping AVFS Architecture on a 32 nm GALS MPSoC. IEEE J. Solid State Circuits Ivan Miro Panades, Edith Beigné, Yvain Thonnart, Laurent Alacoque, Pascal Vivet, Suzanne Lesecq, Diego Puschini, Anca Molnos, Farhat Thabet, Benoît Tain, Karim Ben Chehida, Sylvain Engels, Robin Wilson, Didier Fuin
2013	—	`conf`	A fine grain variation-aware dynamic Vdd-hopping AVFS architecture on a 32nm GALS MPSoC. ESSCIRC Edith Beigné, Ivan Miro-Panades, Yvain Thonnart, Laurent Alacoque, Pascal Vivet, Suzanne Lesecq, Diego Puschini, Farhat Thabet, Benoît Tain, K. Benchehida, Sylvain Engels, Robin Wilson, Didier Fuin
2010	—	`conf`	A Self-reconfigurable FPGA-Based Platform for Prototyping Future Pervasive Systems. ICES Jean-Marc Philippe, Benoît Tain, Christian Gamrat