Benoit Nadeau-Dostie

32 papers A 13B 2Misc 2Journal 9Unranked 5
YearRankTypeTitle / Venue / Authors
2024 B conf
Combining Built-In Redundancy Analysis with ECC for Memory Testing.
ETS
Luc Romain, Paul-Patrick Nordmann, Benoit Nadeau-Dostie, Lori Schramm, Martin Keim
2023 A conf
Transitioning eMRAM from Pilot Project to Volume Production.
ITC
Cyrille Dray, Khushal Gelda, Benoit Nadeau-Dostie, Wei Zou, Luc Romain, Jongsin Yun, Harshitha Kodali, Lori Schramm, Martin Keim
2022 A conf
Configurable BISR Chain For Fast Repair Data Loading.
ITC
Wei Zou, Benoit Nadeau-Dostie
2020 B conf
MBIST Support for Reliable eMRAM Sensing.
ETS
Jongsin Yun, Benoit Nadeau-Dostie, Martin Keim, Cyrille Dray, El Mehdi Boujamaa
2020 A conf
MBIST Supported Multi Step Trim for Reliable eMRAM Sensing.
ITC
Jongsin Yun, Benoit Nadeau-Dostie, Martin Keim, Lori Schramm, Cyrille Dray, El Mehdi Boujamaa, Khushal Gelda
2020 A conf
Memory repair logic sharing techniques and their impact on yield.
ITC
Benoit Nadeau-Dostie, Luc Romain
2018 — conf
Implementing Design-for-Test Within a Tile-Based Design Methodology - Challenges and Solutions.
ITC-Asia
Venkat Yellapragada, Suresh Raman, Banadappa Shivaray, Luc Romain, Benoit Nadeau-Dostie, Martin Keim, Jean-Francois Cote, Albert Au, Giri Podichetty, Ashok Anbalan
2017 — conf
Adapting an industrial memory BIST solution for testing CAMs.
ITC-Asia
Jais Abraham, Uttam Garg, Glenn Colón-Bonet, Ramesh Sharma, Chennian Di, Benoit Nadeau-Dostie, Etienne Racine, Martin Keim
2015 J jnl
Low-Power Programmable PRPG With Test Compression Capabilities.
IEEE Trans. Very Large Scale Integr. Syst.
Michal Filipek, Grzegorz Mrugalski, Nilanjan Mukherjee, Benoit Nadeau-Dostie, Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer
2014 — ch.
Timing-Aware ATPG.
Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits
Mark Kassab, Benoit Nadeau-Dostie, Xijiang Lin
2012 J jnl
Test Point Insertion with Control Points Driven by Existing Functional Flip-Flops.
IEEE Trans. Computers
Joon-Sung Yang, Nur A. Touba, Benoit Nadeau-Dostie
2012 Misc conf
Test generator with preselected toggling for low power built-in self-test.
VTS
Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski, Benoit Nadeau-Dostie
2011 — conf
Power Aware Embedded Test.
Asian Test Symposium
Xijiang Lin, Elham K. Moghaddam, Nilanjan Mukherjee, Benoit Nadeau-Dostie, Janusz Rajski, Jerzy Tyszer
2009 J jnl
Improved Core Isolation and Access for Hierarchical Embedded Test.
IEEE Des. Test Comput.
Benoit Nadeau-Dostie, Saman Adham, Russell Abbott
2009 — conf
Reducing Test Point Area for BIST through Greater Use of Functional Flip-Flops to Drive Control Points.
DFT
Joon-Sung Yang, Benoit Nadeau-Dostie, Nur A. Touba
2009 A conf
Test point insertion using functional flip-flops to drive control points.
ITC
Joon-Sung Yang, Benoit Nadeau-Dostie, Nur A. Touba
2008 A conf
Power-Aware At-Speed Scan Test Methodology for Circuits with Synchronous Clocks.
ITC
Benoit Nadeau-Dostie, Kiyoshi Takeshita, Jean-Francois Cote
2006 A conf
OCI: Open Compression Interface.
ITC
Bruce Cory, Rohit Kapur, Mick Tegethoff, Mark Kassab, Brion L. Keller, Kee Sup Kim, Dwayne Burek, Steven F. Oakland, Benoit Nadeau-Dostie
2004 — conf
A BIST Algorithm for Bit/Group Write Enable Faults in SRAMs.
MTDT
Saman Adham, Benoit Nadeau-Dostie
2002 A conf
Complete, Contactless I/O Testing - Reaching the Boundary in Minimizing Digital IC Testing Cost.
ITC
Stephen K. Sunter, Benoit Nadeau-Dostie
1999 A conf
An embedded technique for at-speed interconnect testing.
ITC
Benoit Nadeau-Dostie, Jean-Francois Cote, Harry Hulvershorn, Stephen Pateras
1999 J jnl
Testability analysis and test-point insertion in RTL VHDL specifications for scan-based BIST.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Samir Boubezari, Eduard Cerny, Bozena Kaminska, Benoit Nadeau-Dostie
1996 J jnl
Built-In Self-Test: Assuring System Integrity.
Computer
Bernd Könemann, Ben Bennetts, Najmi T. Jarwala, Benoit Nadeau-Dostie
1995 A conf
A New Hardware Fault Insertion Scheme for System Diagnostics Verification.
ITC
Benoit Nadeau-Dostie, Harry Hulvershorn, Saman Adham
1994 J jnl
ScanBist: A Multifrequency Scan-Based BIST Method.
IEEE Des. Test Comput.
Benoit Nadeau-Dostie, Dwayne Burek, Abu S. M. Hassan
1993 J jnl
A 180 MHz 0.8 mu m BiCMOS modular memory family of DRAM and multiport SRAM.
IEEE J. Solid State Circuits
Allan L. Silburt, Richard S. Phillips, G. F. Randall Gibson, Steven W. Wood, Armin G. Bluschke, James S. Fujimoto, Stephen P. Kornachuk, Benoit Nadeau-Dostie, Rajesh K. Verma, Peter M. J. Diedrich
1992 J jnl
BIST of PCB interconnects using boundary-scan architecture.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Abu S. M. Hassan, Vinod K. Agarwal, Benoit Nadeau-Dostie, Janusz Rajski
1992 Misc conf
Scan testing of latch arrays.
VTS
Michael M. Y. Hui, Benoit Nadeau-Dostie
1992 A conf
ScanBIST: A Multi-frequency Scan-based BIST Method.
ITC
Benoit Nadeau-Dostie, Dwayne Burek, Abu S. M. Hassan
1990 A conf
A new procedure for weighted random built-in self-test.
ITC
Fidel Muradali, Vinod K. Agarwal, Benoit Nadeau-Dostie
1990 J jnl
Serial Interfacing for Embedded-Memory Testing.
IEEE Des. Test Comput.
Benoit Nadeau-Dostie, Allan Silburt, Vinod K. Agarwal
1989 A conf
Testing of Glue Logic Interconnects Using Boundary Scan Architecture.
ITC
Abu S. M. Hassan, Vinod K. Agarwal, Janusz Rajski, Benoit Nadeau-Dostie