Benno Stabernack

45 papers A 1B 4C 3Journal 12Unranked 24
YearRankTypeTitle / Venue / Authors
2025 — conf
On the Usability and Energy Efficiency of High-Level Synthesis for FPGA-based Network-Attached Accelerators.
IPDPS (Workshops)
Steffen Christgau, Dylan Everingham, Max Lübke, Marco De Lucia, Danny Puhan, Niklas Schelten, Bettina Schnor, Hannes Signer, Johannes Spazier, Benno Stabernack, Fritjof Steinert, Serhii Yahdzhyiev
2025 C conf
UNNIP: Memory Optimized Universal Neural Network Intra-Prediction for Custom On-Chip Hardware-Architectures.
PCS
Viktor Herrmann, Justin Knapheide, Benno Stabernack
2024 — conf
An Approach Towards Distributed DNN Training on FPGA Clusters.
ARCS
Philipp Kreowsky, Justin Knapheide, Benno Stabernack
2024 — ed.
Architecture of Computing Systems - 37th International Conference, ARCS 2024, Potsdam, Germany, May 14-16, 2024, Proceedings
ARCS
Dietmar Fey, Benno Stabernack, Stefan Lankes, Mathias Pacher, Thilo Pionteck
2023 J jnl
A High-Throughput, Resource-Efficient Implementation of the RoCEv2 Remote DMA Protocol and its Application.
ACM Trans. Reconfigurable Technol. Syst.
Niklas Schelten, Fritjof Steinert, Justin Knapheide, Anton Schulte, Benno Stabernack
2023 B conf
Challenges Using FPGA Clusters for Distributed CNN Training.
FPL
Philipp Kreowsky, Justin Knapheide, Benno Stabernack
2023 B conf
Demonstrating NADA: A Workflow for Distributed CNN Training on FPGA Clusters.
FPL
Justin Knapheide, Philipp Kreowsky, Benno Stabernack
2023 — conf
Enabling Communication with FPGA-based Network-attached Accelerators for HPC Workloads.
SC Workshops
Steffen Christgau, Dylan Everingham, Florian Mikolajczak, Niklas Schelten, Bettina Schnor, Max Schrötter, Benno Stabernack, Fritjof Steinert
2023 — conf
FPGA-Based Network-Attached Accelerators - An Environmental Life Cycle Perspective.
ARCS
Fritjof Steinert, Benno Stabernack
2022 C conf
A YOLO v3-tiny FPGA Architecture using a Reconfigurable Hardware Accelerator for Real-time Region of Interest Detection.
DSD
Viktor Herrmann, Justin Knapheide, Fritjof Steinert, Benno Stabernack
2022 J jnl
Architecture of a Low Latency H.264/AVC Video Codec for Robust ML based Image Classification.
J. Signal Process. Syst.
Fritjof Steinert, Benno Stabernack
2022 — conf
Towards an optimal right-turn assistant system to avoid accidents with vulnerable traffic participants.
MECO
Michal Stec, Benno Stabernack, Clemens Kubach
2021 J jnl
A Full-Featured FPGA-Based Pipelined Architecture for SIFT Extraction.
IEEE Access
Philipp Kreowsky, Benno Stabernack
2021 — conf
Architecture of a Low Latency H.264/AVC Video Codec for robust ML based Image Classification.
DASIP
Benno Stabernack, Fritjof Steinert
2021 B conf
Demonstration of a Distributed Accelerator Framework for Energy-efficient ML Processing.
FPL
Fritjof Steinert, Justin Knapheide, Benno Stabernack
2020 — conf
A Hardware/Software Framework for the Integration of FPGA-based Accelerators into Cloud Computing Infrastructures.
SmartCloud
Fritjof Steinert, Philipp Kreowsky, Eric L. Wisotzky, Christian Unger, Benno Stabernack
2020 B conf
A High Throughput MobileNetV2 FPGA Implementation Based on a Flexible Architecture for Depthwise Separable Convolution.
FPL
Justin Knapheide, Benno Stabernack, Maximilian Kuhnke
2020 — conf
A High-Throughput, Resource-Efficient Implementation of the RoCEv2 Remote DMA Protocol for Network-Attached Hardware Accelerators.
FPT
Niklas Schelten, Fritjof Steinert, Anton Schulte, Benno Stabernack
2020 C conf
Hardware and Software Components towards the Integration of Network-Attached Accelerators into Data Centers.
DSD
Fritjof Steinert, Niklas Schelten, Anton Schulte, Benno Stabernack
2019 — conf
Multi-Sensor-Fusion System for People Counting Applications.
SA
Michal Stec, Viktor Herrmann, Benno Stabernack
2019 — conf
Using Time-of-Flight Sensors for People Counting Applications.
DASIP
Michal Stec, Viktor Herrmann, Benno Stabernack
2018 J jnl
Modeling the Energy Consumption of the HEVC Decoding Process.
IEEE Trans. Circuits Syst. Video Technol.
Christian Herglotz, Dominic Springer, Marc Reichenbach, Benno Stabernack, André Kaup
2017 J jnl
Simulation-based HW/SW co-exploration of the concurrent execution of HEVC intra encoding algorithms for heterogeneous multi-core architectures.
J. Syst. Archit.
Jens Brandenburg, Benno Stabernack
2015 — conf
Demonstrating an FPGA implementation of a full HD real-time HEVC decoder with memory optimizations for range extensions support.
DASIP
Benno Stabernack, Jan Moller, Jan Hahlbeck, Jens Brandenburg
2015 — conf
Exploring the concurrent execution of HEVC intra encoding algorithms for heterogeneous multi core architectures.
DASIP
Jens Brandenburg, Benno Stabernack
2014 — conf
A 4k capable FPGA based high throughput binary arithmetic decoder for H.265/MPEG-HEVC.
ICCE-Berlin
Jan Hahlbeck, Benno Stabernack
2014 J jnl
Architectural Decomposition of Video Decoders by Meansof an Intermediate Data Stream Format.
J. Signal Process. Syst.
Henryk Richter, Benno Stabernack, Volker Kühn
2014 J jnl
FPGA implementation of a full HD real-time HEVC main profile decoder.
IEEE Trans. Consumer Electron.
Denis Engelhardt, Jan Moller, Jan Hahlbeck, Benno Stabernack
2014 J jnl
Hardware implementation of a full HD real-time disparity estimation algorithm.
IEEE Trans. Consumer Electron.
Martin Werner, Benno Stabernack, Christian Riechert
2013 J jnl
Architecture of a Low Latency Image Rectification Engine for Stereoscopic 3-D HDTV Processing.
IEEE Trans. Circuits Syst. Video Technol.
Heiko Hübert, Benno Stabernack, Frederik Zilly
2013 — conf
Memory access analysis and optimization of a parallel H.264/SVC decoder for an embedded multi-core platform.
DASIP
Jens Brandenburg, Benno Stabernack
2012 — conf
A Generic and Non-intrusive Profiling Methodology for SystemC Multi-core Platform Simulation Models.
ARCS
Jens Brandenburg, Benno Stabernack
2012 — conf
Architectural decomposition of video decoders for many core architectures.
DASIP
Henryk Richter, Benno Stabernack, Volker Kühn
2012 — conf
Parallel paradigms and run-time management techniques for many-core architectures: the 2PARMA approach.
INA-OCMC@HiPEAC
Cristina Silvano, William Fornaciari, Stefano Crespi-Reghizzi, Giovanni Agosta, Gianluca Palermo, Vittorio Zaccaria, Patrick Bellasi, Fabrizio Castro, Simone Corbetta, Ettore Speziale, Diego Melpignano, J. M. Zins, David Siorpaes, Heiko Hübert, Benno Stabernack, Jens Brandenburg, Martin Palkovic, Praveen Raghavan, Chantal Ykman-Couvreur, Alexandros Bartzas, Dimitrios Soudris, Torsten Kempf, Gerd Ascheid, Heinrich Meyr, Junaid Ansari, Petri Mähönen, Bart Vanthournout
2011 — conf
Invited paper: Parallel programming and run-time resource management framework for many-core platforms: The 2PARMA approach.
ReCoSoC
Cristina Silvano, William Fornaciari, Stefano Crespi-Reghizzi, Giovanni Agosta, Gianluca Palermo, Vittorio Zaccaria, Patrick Bellasi, Fabrizio Castro, Simone Corbetta, Ettore Speziale, Diego Melpignano, J. M. Zins, Heiko Hübert, Benno Stabernack, Jens Brandenburg, Martin Palkovic, Praveen Raghavan, Chantal Ykman-Couvreur, Iraklis Anagnostopoulos, Alexandros Bartzas, Dimitrios Soudris, Torsten Kempf, Gerd Ascheid, Junaid Ansari, Petri Mähönen, Bart Vanthournout
2010 — conf
2PARMA: Parallel Paradigms and Run-Time Management Techniques for Many-Core Architectures.
ISVLSI
Cristina Silvano, William Fornaciari, Stefano Crespi-Reghizzi, Giovanni Agosta, Gianluca Palermo, Vittorio Zaccaria, Patrick Bellasi, Fabrizio Castro, Simone Corbetta, Andrea Di Biagio, Ettore Speziale, Michele Tartara, David Siorpaes, Heiko Hübert, Benno Stabernack, Jens Brandenburg, Martin Palkovic, Praveen Raghavan, Chantal Ykman-Couvreur, Alexandros Bartzas, Sotirios Xydis, Dimitrios Soudris, Torsten Kempf, Gerd Ascheid, Rainer Leupers, Heinrich Meyr, Junaid Ansari, Petri Mähönen, Bart Vanthournout
2010 — conf
2PARMA: Parallel Paradigms and Run-time Management Techniques for Many-Core Architectures.
ISVLSI (Selected papers)
Cristina Silvano, William Fornaciari, Stefano Crespi-Reghizzi, Giovanni Agosta, Gianluca Palermo, Vittorio Zaccaria, Patrick Bellasi, Fabrizio Castro, Simone Corbetta, Andrea Di Biagio, Ettore Speziale, Michele Tartara, Diego Melpignano, J. M. Zins, David Siorpaes, Heiko Hübert, Benno Stabernack, Jens Brandenburg, Martin Palkovic, Praveen Raghavan, Chantal Ykman-Couvreur, Alexandros Bartzas, Sotirios Xydis, Dimitrios Soudris, Torsten Kempf, Gerd Ascheid, Rainer Leupers, Heinrich Meyr, Junaid Ansari, Petri Mähönen, Bart Vanthournout
2009 — conf
Power Modeling of an Embedded RISC Core for Function-Accurate Energy Profiling.
MBMV
Heiko Hübert, Benno Stabernack
2009 J jnl
Profiling-Based Hardware/Software Co-Exploration for the Design of Video Coding Architectures.
IEEE Trans. Circuits Syst. Video Technol.
Heiko Hübert, Benno Stabernack
2008 — conf
Generic algorithms for motion compensation and transformation.
Real-Time Image Processing
Henryk Richter, Benno Stabernack, Erika Müller
2007 J jnl
A System on a Chip Architecture of an H.264/AVC Coprocessor for DVB-H and DMB Applications.
IEEE Trans. Consumer Electron.
Benno Stabernack, Kai-Immo Wels, Heiko Hübert
2007 — conf
Performance and Memory Profiling for Embedded System Design.
SIES
Heiko Hübert, Benno Stabernack, Kai-Immo Wels
2004 — conf
Tool-aided performance analysis and optimization of multimedia applications.
ESTIMedia
Heiko Hübert, Benno Stabernack, Henryk Richter
2003 A conf
A system for QOS-enabled MPEG-4 video transmission over Bluetooth for mobile applications.
ICME
Corina Scheiter, Rainer Steffen, Markus Zeller, Rudi Knorr, Benno Stabernack, Kai-Immo Wels
1999 J jnl
Instruction Set Extensions for MPEG-4 Video.
J. VLSI Signal Process.
Mladen Berekovic, Hans-Joachim Stolberg, Mark Bernd Kulaczewski, Peter Pirsch, Henning Möller, Holger Runge, Johannes Kneip, Benno Stabernack