Benjamín T. Reyes

27 papers C 5Journal 9Unranked 13

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	An Eight-Lane 800-Gb/s Transceiver for PAM-4 Optical Direct-Detection Applications in 5-nm FinFET Process. IEEE J. Solid State Circuits Fabio Giunco, Marco Sosio, Claudio Nani, Ivan Fabiano, Travis Lovitt, Victor Karam, Domenico Albano, Claudio Asero, Nicola Codega, Marco Garampazzi, Nicola Ghittori, Leonardo Daniel Herbas Burgos, Stanley S. K. Ho, Enrico Monaco, Benjamín T. Reyes, Paolo Rossi, Enrico Temporiti, Paolo Pascale, Fernando De Bernardinis, Shawn Scouten, Stephen Jantzi
2024	—	`conf`	18.3 An 8b 160GS/s 57GHz Bandwidth Time-Interleaved DAC and Driver-Based Transmitter with Adaptive Calibration for 800Gb/s Coherent Optical Applications in 5nm. ISSCC F. Ahmad, A. Mellati, A. Fernandez, A. Iyer, A. Fan, Benjamín T. Reyes, Cindra Abidin, Claudio Nani, D. Albano, Fredy Solis, Gabriele Minoia, Geoff Hatcher, Hugo S. Carrer, K. Kota, L. Wang, M. Bachu, Marco Garampazzi, M. Hassanpourghadi, N. Fan, P. Prabha, R. L. Nguyen, S. Ho, T. Dusatko, T. Wu, W. Elsharkasy, Z. Sun, S. Jantzi, L. Tse
2024	—	`conf`	18.4 A 200GS/s 8b 20fJ/c-s Receiver with >60GHz AFE Bandwidth for 800Gb/s Optical Coherent Communications in 5nm FinFET. ISSCC R. L. Nguyen, A. Mellati, A. Fernandez, A. Iyer, A. Fan, Benjamín T. Reyes, Cindra Abidin, Claudio Nani, D. Albano, F. Ahmad, Fredy Solis, Gabriele Minoia, Geoff Hatcher, M. Bachu, Marco Garampazzi, Mohsen Hassanpourghadi, N. Fan, P. Prabha, S. Fan, S. Ho, T. Dusatko, Tzu-Fan Wu, W. Elsharkasy, Z. Sun, S. Jantzi, L. Tse
2024	—	`conf`	A 800Gb/s Transceiver for PAM-4 Optical Direct-Detection Applications in 5nm FinFet Process. VLSI Technology and Circuits Fabio Giunco, Marco Sosio, Claudio Nani, Ivan Fabiano, Travis Lovitt, Victor Karam, D. Albano, C. Asero, Nicola Codega, Marco Garampazzi, Nicola Ghittori, D. Herbas, S. Ho, Enrico Monaco, Benjamín T. Reyes, P. Rossi, E. Temporiti, P. Pascale, Fernando De Bernardinis, S. Scouten, S. Jantzi
2023	J	`jnl`	Adaptive Digital Compensation of Analog Impairments in Frequency Interleaved ADC for Next-Generation High-Speed Communication Receivers. IEEE Access Leandro Passetti, Damián A. Morero, Benjamín T. Reyes, Mario R. Hueda
2023	J	`jnl`	Digital Background Compensation of Analog Impairments in Jointly Frequency-Time Interleaved DACs. IEEE Access Agustin C. Galetto, Juan I. Bonetti, Benjamín T. Reyes, Damián A. Morero, Mario R. Hueda
2023	—	`conf`	Evaluation of the Performance Impact of Clock Jitter and Phase Noise in a Two-Band Frequency-Interleaved ADC. ICECS Leandro Passetti, Benjamín T. Reyes, Damián A. Morero, Mario R. Hueda
2022	—	`conf`	Backpropagation Based Background Compensation of TI-DAC Errors in High-Speed Transmitters. MWSCAS Agustin C. Galetto, Benjamín T. Reyes, Damián A. Morero, Mario R. Hueda
2022	J	`jnl`	Error-Backpropagation-Based Background Calibration of TI-ADC for Adaptively Equalized Digital Communication Receivers. IEEE Access Fredy Solis, Benjamín T. Reyes, Damián A. Morero, Mario R. Hueda
2022	—	`conf`	Reduced Complexity Adaptive Background Compensation of Electro-Optic Tx Impairments in Coherent Optical Transceivers. OFC James Kunst, Juan I. Bonetti, Benjamín T. Reyes, Damián A. Morero, Mario R. Hueda
2021	—	`conf`	8.6 A Highly Reconfigurable 40-97GS/s DAC and ADC with 40GHz AFE Bandwidth and Sub-35fJ/conv-step for 400Gb/s Coherent Optical Applications in 7nm FinFET. ISSCC R. L. Nguyen, A. M. Castrillon, A. Fan, A. Mellati, Benjamín T. Reyes, Cindra Abidin, E. Olsen, F. Ahmad, Geoff Hatcher, J. Chana, Laura Biolato, L. Tse, L. Wang, M. Azarmnia, Mehdi Davoodi, N. Campos, N. Fan, P. Prabha, Q. Lu, S. Cyrusian, S. Dallaire, S. Ho, S. Jantzi, T. Dusatko, W. Elsharkasy
2021	J	`jnl`	A 4GS/s 8-bit time-interleaved SAR ADC with an energy-efficient architecture in 130 nm CMOS. Int. J. Circuit Theory Appl. Fredy Solis, Álvaro Fernandez Bocco, Agustin C. Galetto, Leandro Passetti, Mario R. Hueda, Benjamín T. Reyes
2021	J	`jnl`	Adaptive Background Compensation of Frequency Interleaved DACs With Application to Coherent Optical Transceivers. IEEE Access Agustin C. Galetto, Benjamín T. Reyes, Damián A. Morero, Mario R. Hueda
2021	—	`conf`	An Error Backpropagation-based Background Calibration of Pipeline TI-ADCs for 256-QAM Optical Coherent Receivers. LASCAS Álvaro Fernandez Bocco, Fredy Solis, Benjamín T. Reyes, Damián A. Morero, Mario R. Hueda
2021	—	`conf`	Background Compensation of Frequency Interleaved DAC for Optical Transceivers. LASCAS Agustin C. Galetto, Benjamín T. Reyes, Damián A. Morero, Mario R. Hueda
2021	C	`conf`	Experimental Evaluation of Backpropagation-Based Background Compensation of TI-ADC with Application to Digital Communication Receivers. ISCAS Fredy Solis, Damián A. Morero, Mario R. Hueda, Benjamín T. Reyes
2021	C	`conf`	Reduced Complexity Backpropagation-Based Adaptive Compensation of Frequency Interleaved ADC for Digital Communication Receivers. ISCAS Leandro Passetti, Benjamín T. Reyes, Damián A. Morero, Mario R. Hueda
2020	C	`conf`	Background Calibration of Time-Interleaved ADC for Optical Coherent Receivers using Error Backpropagation Techniques. ISCAS Fredy Solis, Álvaro Fernandez Bocco, Damián A. Morero, Mario R. Hueda, Benjamín T. Reyes
2020	C	`conf`	Backpropagation-Based Background Compensation of Frequency Interleaved ADC for Coherent Optical Receivers. ISCAS Leandro Passetti, Agustin C. Galetto, Diego J. Hernando, Damián A. Morero, Benjamín T. Reyes, Mario R. Hueda
2019	J	`jnl`	An Energy-Efficient Hierarchical Architecture for Time-Interleaved SAR ADC. IEEE Trans. Circuits Syst. I Regul. Pap. Benjamín T. Reyes, Laura Biolato, Agustin C. Galetto, Leandro Passetti, Fredy Solis, Mario R. Hueda
2018	—	`conf`	An 8-bit 3.2GS/S CMOS time-interleaved SAR ADC with non-buffered input demultiplexing. LASCAS Benjamín T. Reyes, Laura Biolato, Agustin C. Galetto, Leandro Passetti, Fredy Solis, Mario R. Hueda
2017	J	`jnl`	Design and Experimental Evaluation of a Time-Interleaved ADC Calibration Algorithm for Application in High-Speed Communication Systems. IEEE Trans. Circuits Syst. I Regul. Pap. Benjamín T. Reyes, Raul M. Sanchez, Ariel L. Pola, Mario R. Hueda
2016	—	`conf`	An FPGA-based emulation platform for evaluation of time-interleaved ADC calibration systems. LASCAS Raul M. Sanchez, Benjamín T. Reyes, Ariel L. Pola, Mario Rafael Hueda
2016	J	`jnl`	Efficient Estimation and Correction of Mismatch Errors in Time-Interleaved ADCs. IEEE Trans. Instrum. Meas. Christian A. Schmidt, Juan E. Cousseau, José Luis Figueroa, Benjamín T. Reyes, Mario R. Hueda
2014	—	`conf`	A 1.6Gb/s CMOS LVDS transmitter with a programmable pre-emphasis system. LASCAS Benjamín T. Reyes, German Paulina, Lucas Tealdi, Emanuel Labat, Raul M. Sanchez, Pablo Sergio Mandolesi, Mario Rafael Hueda
2014	—	`conf`	A 6-bit 2GS/s CMOS time-interleaved ADC for analysis of mixed-signal calibration techniques. LASCAS Benjamín T. Reyes, Lucas Tealdi, German Paulina, Emanuel Labat, Raul M. Sanchez, Pablo Sergio Mandolesi, Mario Rafael Hueda
2012	C	`conf`	Joint sampling-time error and channel skew calibration of time-interleaved ADC in multichannel fiber optic receivers. ISCAS Benjamín T. Reyes, Venu Gopinathan, Pablo Sergio Mandolesi, Mario R. Hueda