Benjamin P. Hershberg

39 papers C 2Journal 16Unranked 21

Year	Rank	Type	Title / Venue / Authors
2024	J	`jnl`	A 4.6-400 K Functional Ringamp-Based 250 MS/s 12 b Pipelined ADC With PVT-Robust Unity-Gain-Frequency-Aware Bias Calibration. IEEE J. Solid State Circuits Kaoru Yamashita, Benjamin P. Hershberg, Kentaro Yoshioka, Hiroki Ishikuro
2023	—	`conf`	A 4.6K to 400K Functional PVT-Robust Ringamp-Based 250MS/s 12b Pipelined ADC with Pole-Aware Bias Calibration. CICC Kaoru Yamashita, Benjamin P. Hershberg, Kentaro Yoshioka, Hiroki Ishikuro
2022	J	`jnl`	A 10.1-ENOB, 6.2-fJ/conv.-step, 500-MS/s, Ringamp-Based Pipelined-SAR ADC With Background Calibration and Dynamic Reference Regulation in 16-nm CMOS. IEEE J. Solid State Circuits Jorge Lagos, Nereo Markulic, Benjamin P. Hershberg, Davide Dermit, Mithlesh Shrivas, Ewout Martens, Jan Craninckx
2022	J	`jnl`	A 950 MHz Clock 47.5 MHz BW 4.7 mW 67 dB SNDR Discrete Time Delta Sigma ADC Leveraging Ring Amplification and Split-Source Comparator Based Quantizer in 28 nm CMOS. IEEE J. Solid State Circuits Lucas Moura Santana, Ewout Martens, Jorge Lagos, Benjamin P. Hershberg, Piet Wambacq, Jan Craninckx
2021	J	`jnl`	A 1-MS/s to 1-GS/s Ringamp-Based Pipelined ADC With Fully Dynamic Reference Regulation and Stochastic Scope-on-Chip Background Monitoring in 16 nm. IEEE J. Solid State Circuits Benjamin P. Hershberg, Nereo Markulic, Jorge Lagos, Ewout Martens, Davide Dermit, Jan Craninckx
2021	—	`conf`	A 10.0 ENOB, 6.2 fJ/conv.-step, 500 MS/s Ringamp-Based Pipelined-SAR ADC with Background Calibration and Dynamic Reference Regulation in 16nm CMOS. VLSI Circuits Jorge Lagos, Nereo Markulic, Benjamin P. Hershberg, Davide Dermit, Mithlesh Shrivas, Ewout Martens, Jan Craninckx
2021	J	`jnl`	A 4-GS/s 10-ENOB 75-mW Ringamp ADC in 16-nm CMOS With Background Monitoring of Distortion. IEEE J. Solid State Circuits Benjamin P. Hershberg, Davide Dermit, Barend van Liempd, Ewout Martens, Nereo Markulic, Jorge Lagos, Jan Craninckx
2021	—	`conf`	A 47.5MHz BW 4.7mW 67dB SNDR Ringamp Based Discrete-Time Delta Sigma ADC. ESSCIRC Lucas Moura Santana, Ewout Martens, Jorge Lagos, Benjamin P. Hershberg, Piet Wambacq, Jan Craninckx
2021	J	`jnl`	Asynchronous Event-Driven Clocking and Control in Pipelined ADCs. IEEE Trans. Circuits Syst. I Regul. Pap. Benjamin P. Hershberg, Barend van Liempd, Nereo Markulic, Jorge Lagos, Ewout Martens, Davide Dermit, Jan Craninckx
2020	—	`conf`	A 1MS/s to 1GS/s Ringamp-Based Pipelined ADC with Fully Dynamic Reference Regulation and Stochastic Scope-on-Chip Background Monitoring in 16nm. VLSI Circuits Benjamin P. Hershberg, Nereo Markulic, Jorge Lagos, Ewout Martens, Davide Dermit, Jan Craninckx
2019	J	`jnl`	A 1-GS/s, 12-b, Single-Channel Pipelined ADC With Dead-Zone-Degenerated Ring Amplifiers. IEEE J. Solid State Circuits Jorge Lagos, Benjamin P. Hershberg, Ewout Martens, Piet Wambacq, Jan Craninckx
2019	—	`conf`	A 3.2GS/s 10 ENOB 61mW Ringamp ADC in 16nm with Background Monitoring of Distortion. ISSCC Benjamin P. Hershberg, Davide Dermit, Barend van Liempd, Ewout Martens, Nereo Markulic, Jorge Lagos, Jan Craninckx
2019	—	`conf`	A 6-to-600MS/s Fully Dynamic Ringamp Pipelined ADC with Asynchronous Event-Driven Clocking in 16nm. ISSCC Benjamin P. Hershberg, Barend van Liempd, Nereo Markulic, Jorge Lagos, Ewout Martens, Davide Dermit, Jan Craninckx
2019	J	`jnl`	A Single-Channel, 600-MS/s, 12-b, Ringamp-Based Pipelined ADC in 28-nm CMOS. IEEE J. Solid State Circuits Jorge Lagos, Benjamin P. Hershberg, Ewout Martens, Piet Wambacq, Jan Craninckx
2018	—	`conf`	A 1Gsps, 12-bit, single-channel pipelined ADC with dead-zone-degenerated ring amplifiers. CICC Jorge Lagos, Benjamin P. Hershberg, Ewout Martens, Piet Wambacq, Jan Craninckx
2018	J	`jnl`	A 69-dB SNDR 300-MS/s Two-Time Interleaved Pipelined SAR ADC in 16-nm CMOS FinFET With Capacitive Reference Stabilization. IEEE J. Solid State Circuits Ewout Martens, Benjamin P. Hershberg, Jan Craninckx
2016	—	`conf`	20.8 A dual-frequency 0.7-to-1GHz balance network for electrical balance duplexers. ISSCC Benjamin P. Hershberg, Barend van Liempd, Xiaoqiang Zhang, Piet Wambacq, Jan Craninckx
2016	—	`conf`	9.7 A self-calibrated 10Mb/s phase modulator with -37.4dB EVM based on a 10.1-to-12.4GHz, -246.6dB-FOM, fractional-N subsampling PLL. ISSCC Nereo Markulic, Kuba Raczkowski, Ewout Martens, Pedro Emiliano Paro Filho, Benjamin P. Hershberg, Piet Wambacq, Jan Craninckx
2016	J	`jnl`	A DTC-Based Subsampling PLL Capable of Self-Calibrated Fractional Synthesis and Two-Point Modulation. IEEE J. Solid State Circuits Nereo Markulic, Kuba Raczkowski, Ewout Martens, Pedro Emiliano Paro Filho, Benjamin P. Hershberg, Piet Wambacq, Jan Craninckx
2015	—	`conf`	2.2 A +70dBm IIP3 single-ended electrical-balance duplexer in 0.18um SOI CMOS. ISSCC Barend van Liempd, Benjamin P. Hershberg, Kuba Raczkowski, Saneaki Ariumi, Udo Karthaus, Karl-Frederik Bink, Jan Craninckx
2015	J	`jnl`	A 9.2-12.7 GHz Wideband Fractional-N Subsampling PLL in 28 nm CMOS With 280 fs RMS Jitter. IEEE J. Solid State Circuits Kuba Raczkowski, Nereo Markulic, Benjamin P. Hershberg, Jan Craninckx
2015	—	`conf`	An electrical-balance duplexer for in-band full-duplex with <-85dBm in-band distortion at +10dBm TX-power. ESSCIRC Barend van Liempd, Benjamin P. Hershberg, Björn Debaillie, Piet Wambacq, Jan Craninckx
2015	—	`conf`	In-band full-duplex transceiver technology for 5G mobile networks. ESSCIRC Björn Debaillie, Barend van Liempd, Benjamin P. Hershberg, Jan Craninckx, Kari Rikkinen, D. J. van den Broek, Eric A. M. Klumperink, Bram Nauta
2015	—	`conf`	Real-time RF self-interference cancellation for in-band full duplex. DySPAN Tom Vermeulen, Barend van Liempd, Benjamin P. Hershberg, Sofie Pollin
2014	—	`conf`	A 9.1-12.7 GHz VCO in 28nm CMOS with a bottom-pinning bias technique for digital varactor stress reduction. ESSCIRC Benjamin P. Hershberg, Kuba Raczkowski, Kristof Vaesen, Jan Craninckx
2014	J	`jnl`	Digitally Synthesized Stochastic Flash ADC Using Only Standard Digital Cells. IEEE Trans. Circuits Syst. I Regul. Pap. Skyler Weaver, Benjamin P. Hershberg, Un-Ku Moon
2013	—	`conf`	Parallel gain enhancement technique for switched-capacitor circuits. CICC Hariprasath Venkatram, Benjamin P. Hershberg, Taehwan Oh, Manideep Gande, Kazuki Sobue, Koichi Hamashita, Un-Ku Moon
2012	—	`conf`	A 61.5dB SNDR pipelined ADC using simple highly-scalable ring amplifiers. VLSIC Benjamin P. Hershberg, Skyler Weaver, Kazuki Sobue, Seiji Takeuchi, Koichi Hamashita, Un-Ku Moon
2012	J	`jnl`	Ring Amplifiers for Switched Capacitor Circuits. IEEE J. Solid State Circuits Benjamin P. Hershberg, Skyler Weaver, Kazuki Sobue, Seiji Takeuchi, Koichi Hamashita, Un-Ku Moon
2012	—	`conf`	Ring amplifiers for switched-capacitor circuits. ISSCC Benjamin P. Hershberg, Skyler Weaver, Kazuki Sobue, Seiji Takeuchi, Koichi Hamashita, Un-Ku Moon
2012	C	`conf`	The effect of correlated level shifting on noise performance in switched capacitor circuits. ISCAS Benjamin P. Hershberg, Tawfiq Musah, Skyler Weaver, Un-Ku Moon
2011	C	`conf`	Binary Access Memory: An optimized lookup table for successive approximation applications. ISCAS Benjamin P. Hershberg, Skyler Weaver, Seiji Takeuchi, Koichi Hamashita, Un-Ku Moon
2011	J	`jnl`	Domino-Logic-Based ADC for Digital Synthesis. IEEE Trans. Circuits Syst. II Express Briefs Skyler Weaver, Benjamin P. Hershberg, Nima Maghari, Un-Ku Moon
2010	—	`conf`	A 1.4V signal swing hybrid CLS-opamp/ZCBC pipelined ADC using a 300mV output swing opamp. ISSCC Benjamin P. Hershberg, Skyler Weaver, Un-Ku Moon
2010	—	`conf`	Asynchronous CLS for Zero Crossing based Circuits. ICECS Hariprasath Venkatram, Benjamin P. Hershberg, Un-Ku Moon
2010	J	`jnl`	Design of a Split-CLS Pipelined ADC With Full Signal Swing Using an Accurate But Fractional Signal Swing Opamp. IEEE J. Solid State Circuits Benjamin P. Hershberg, Skyler Weaver, Un-Ku Moon
2010	—	`conf`	PDF folding for stochastic flash ADCs. ICECS Skyler Weaver, Benjamin P. Hershberg, Un-Ku Moon
2010	J	`jnl`	Stochastic Flash Analog-to-Digital Conversion. IEEE Trans. Circuits Syst. I Regul. Pap. Skyler Weaver, Benjamin P. Hershberg, Peter Kurahashi, Daniel Knierim, Un-Ku Moon
2009	—	`conf`	A multiplexer-based digital passive linear counter (PLINCO). ICECS Skyler Weaver, Benjamin P. Hershberg, Pavan Kumar Hanumolu, Un-Ku Moon