Benjamin Carrión Schäfer

105 papers A* 7A 12B 6C 20Misc 3Journal 29Unranked 27

Year	Rank	Type	Title / Venue / Authors
2025	A*	`conf`	ADVISOR: Approximate Computing-frienDly High-LeVel Synthesis DesIgn Space ExplORer. DAC Baharealsadat Parchamdar, Benjamin Carrión Schäfer
2025	—	`conf`	Efficient and Secure Cloud-based Split Logic Synthesis. ASP-DAC Chaitali Sathe, Yiorgos Makris, Benjamin Carrión Schäfer
2025	—	`conf`	HAMMER: Hardware-aware Runtime Program Execution Acceleration through runtime reconfigurable CGRAs. ASP-DAC Qilin Si, Benjamin Carrión Schäfer
2025	—	`conf`	Making Legacy Hardware Robust against Side Channel Attacks via High-Level Synthesis. ASP-DAC Md. Imtiaz Rashid, Benjamin Carrión Schäfer
2024	A*	`conf`	Finding Bugs in RTL Descriptions: High-Level Synthesis to the Rescue. DAC Baharealsadat Parchamdar, Benjamin Carrión Schäfer
2023	—	`conf`	ADVICE: Automatic Design and Optimization of Behavioral Application Specific Processors. ACM Great Lakes Symposium on VLSI Qilin Si, Benjamin Carrión Schäfer
2023	C	`conf`	CERTIFY: AutomatiC MEasuRing The QualIty oF High-Level SYnthesis. ISCAS M. Imtiaz Rashid, Amir H. Torabi, Benjamin Carrión Schäfer
2023	J	`jnl`	I-TAINTED: Identification of Turmeric Adulteration Using the CavIty PerturbatioN Technique and Technology OptimizED Machine Learning. IEEE Access Tejinder Kaur, Axel Gamez, José Luis Olvera-Cervantes, Benjamin Carrión Schäfer, Alonso Corona-Chavez
2023	J	`jnl`	Machine learning based fast and accurate High Level Synthesis design space exploration: From graph to synthesis. Integr. Pingakshya Goswami, Benjamin Carrión Schäfer, Dinesh Bhatia
2023	—	`conf`	PEPA: Performance Enhancement of Embedded Processors through HW Accelerator Resource Sharing. ACM Great Lakes Symposium on VLSI Qilin Si, Benjamin Carrión Schäfer
2022	—	`conf`	Hotspot Mitigation through Multi-Row Thermal-aware Re-Placement of Logic Cells based on High-Level Synthesis Scheduling. ASP-DAC Benjamin Carrión Schäfer
2022	—	`conf`	Improving the Quality of Hardware Accelerators through automatic Behavioral Input Language Conversion in HLS. ASP-DAC M. Imtiaz Rashid, Benjamin Carrión Schäfer
2022	J	`jnl`	Leveraging Automatic High-Level Synthesis Resource Sharing to Maximize Dynamical Voltage Overscaling with Error Control. ACM Trans. Design Autom. Electr. Syst. Prattay Chowdhury, Benjamin Carrión Schäfer
2022	C	`conf`	Modernizing Hardware Circuits through High-Level Synthesis. ISCAS Md. Imtiaz Rashid, Qilin Si, Benjamin Carrión Schäfer
2022	A	`conf`	Predictive Model Attack for Embedded FPGA Logic Locking. ISLPED Prattay Chowdhury, Chaitali Sathe, Benjamin Carrión Schäfer
2021	—	`conf`	Area Efficient Functional Locking through Coarse Grained Runtime Reconfigurable Architectures. ASP-DAC Jianqi Chen, Benjamin Carrión Schäfer
2021	A	`conf`	BEACON: BEst Approximations for Complete BehaviOral HeterogeNeous SoCs. ISLPED Prattay Chowdhury, Benjamin Carrión Schäfer
2021	C	`conf`	Effective High-Level Synthesis Design Space Exploration through a Novel Cost Function Formulation. ISCAS Yiheng Gao, Benjamin Carrión Schäfer
2021	Misc	`conf`	Efficient Hierarchical Post-Silicon Validation and Debug. VLSID Pandy Kalimuthu, Kanad Basu, Benjamin Carrión Schäfer
2021	A*	`conf`	Enabling the Design of Behavioral Systems-on-Chip. DAC Santosh Shetty, Benjamin Carrión Schäfer
2021	C	`conf`	Functional Locking through Omission: From HLS to Obfuscated Design. ICCD Zi Wang, Shayan Omais Mohammed, Yiorgos Makris, Benjamin Carrión Schäfer
2021	A	`conf`	Locking the Re-usability of Behavioral IPs: Discriminating the Search Space through Partial Encryptions. DATE Zi Wang, Benjamin Carrión Schäfer
2021	—	`conf`	Micro-architecture Tuning for Dynamic Frequency Scaling in Coarse-Grain Runtime Reconfigurable Arrays with Adaptive Clock Domain Support. ISVLSI Qilin Si, M. Imtiaz Rashid, Benjamin Carrión Schäfer
2021	C	`conf`	Reducing the Complexity of Fault-Tolerant System Amenable to Approximate Computing. ISCAS Zhiqi Zhu, Benjamin Carrión Schäfer
2021	C	`conf`	Special Session: ADAPT: ANN-ControlleD System-Level Runtime Adaptable APproximate CompuTing. ICCD Prattay Chowdhury, Benjamin Carrión Schäfer
2021	—	`conf`	Unlocking Approximations through Selective Source Code Transformations. ACM Great Lakes Symposium on VLSI Prattay Chowdhury, Benjamin Carrión Schäfer
2021	A	`conf`	Watermarking of Behavioral IPs: A Practical Approach. DATE Jianqi Chen, Benjamin Carrión Schäfer
2020	A	`conf`	An Efficient MILP-Based Aging-Aware Floorplanner for Multi-Context Coarse-Grained Runtime Reconfigurable FPGAs. DATE Bo Hu, Mustafa M. Shihab, Yiorgos Makris, Benjamin Carrión Schäfer, Carl Sechen
2020	C	`conf`	Bespoke Behavioral Processors. ICCD Rohit Sreekumar, Prattay Chowdhury, Benjamin Carrión Schäfer
2020	A*	`conf`	DECOY: DEflection-Driven HLS-Based Computation Partitioning for Obfuscating Intellectual PropertY. DAC Jianqi Chen, Monir Zaman, Yiorgos Makris, R. D. Shawn Blanton, Subhasish Mitra, Benjamin Carrión Schäfer
2020	—	`conf`	Efficient Functional Locking of Behavioral IPs. MWSCAS Anjana Balachandran, Benjamin Carrión Schäfer
2020	A	`conf`	Efficient and Robust High-Level Synthesis Design Space Exploration through offline Micro-kernels Pre-characterization. DATE Zi Wang, Jianqi Chen, Benjamin Carrión Schäfer
2020	J	`jnl`	High-Level Synthesis Design Space Exploration: Past, Present, and Future. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Benjamin Carrión Schäfer, Zi Wang
2020	C	`conf`	Light-Weight Soft-Errors Detection Mechanism in High-Level Synthesis. ISCAS Zhiqi Zhu, Benjamin Carrión Schäfer
2020	A*	`conf`	Machine Leaming to Set Meta-Heuristic Specific Parameters for High-Level Synthesis Design Space Exploration. DAC Zi Wang, Benjamin Carrión Schäfer
2020	A	`conf`	On the Design of High Performance HW Accelerator through High-level Synthesis Scheduling Approximations. DATE Siyuan Xu, Benjamin Carrión Schäfer
2020	J	`jnl`	Predictive Compositional Method to Design and Reoptimize Complex Behavioral Dataflows. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Shuangnan Liu, Francis C. M. Lau, Benjamin Carrión Schäfer
2019	A*	`conf`	Accelerating FPGA Prototyping through Predictive Model-Based HLS Design Space Exploration. DAC Shuangnan Liu, Francis C. M. Lau, Benjamin Carrión Schäfer
2019	A	`conf`	Approximating Behavioral HW Accelerators through Selective Partial Extractions onto Synthesizable Predictive Models. ICCAD Siyuan Xu, Benjamin Carrión Schäfer
2019	A	`conf`	Common-Mode Failure Mitigation: Increasing Diversity through High-Level Synthesis. DATE Farah Naz Taher, Matthew Joslin, Anjana Balachandran, Zhiqi Zhu, Benjamin Carrión Schäfer
2019	A	`conf`	Design Obfuscation through Selective Post-Fabrication Transistor-Level Programming. DATE Mustafa M. Shihab, Jingxiang Tian, Gaurav Rajavendra Reddy, Bo Hu, William Swartz, Benjamin Carrión Schäfer, Carl Sechen, Yiorgos Makris
2019	J	`jnl`	Design space exploration of heterogeneous MPSoCs with variable number of hardware accelerators. Microprocess. Microsystems Siyuan Xu, Shuangnan Liu, Yidi Liu, Anushree Mahapatra, Monica Villaverde, Félix Moreno, Benjamin Carrión Schäfer
2019	Misc	`conf`	Efficient Hardware Acceleration for Design Diversity Calculation to Mitigate Common Mode Failures. FCCM Maheshwaran Ramesh Babu, Farah Naz Taher, Anjana Balachandran, Benjamin Carrión Schäfer
2019	C	`conf`	Exploiting the Benefits of High-Level Synthesis for Thermal-Aware VLSI Design. ICCD Jianqi Chen, Benjamin Carrión Schäfer
2019	—	`conf`	Exploring Design Trade-offs in Fault-Tolerant Behavioral Hardware Accelerators. ACM Great Lakes Symposium on VLSI Zhiqi Zhu, Farah Naz Taher, Benjamin Carrión Schäfer
2019	—	`conf`	Extending the Lifetime of Coarse-Grained Runtime Reconfigurable FPGAs by Balancing Processing Element Usage. FPT Bo Hu, Mustafa M. Shihab, Yiorgos Makris, Benjamin Carrión Schäfer, Carl Sechen
2019	—	`conf`	Functional Obfuscation of Hardware Accelerators through Selective Partial Design Extraction onto an Embedded FPGA. ACM Great Lakes Symposium on VLSI Bo Hu, Jingxiang Tian, Mustafa M. Shihab, Gaurav Rajavendra Reddy, William Swartz, Yiorgos Makris, Benjamin Carrión Schäfer, Carl Sechen
2019	C	`conf`	Learning-Based Diversity Estimation: Leveraging the Power of High-Level Synthesis to Mitigate Common-Mode Failure. ICCD Farah Naz Taher, Anjana Balachandran, Benjamin Carrión Schäfer
2019	C	`conf`	Low Power Design of Runtime Reconfigurable FPGAs through Contexts Approximations. ICCD Siyuan Xu, Benjamin Carrión Schäfer
2019	C	`conf`	Low Power Design through Frequency-Optimized Runtime Micro-Architectural Adaptation. ICCD Jianqi Chen, Benjamin Carrión Schäfer
2019	C	`conf`	Optimizing RTL to C Abstraction Methodologies to Improve HLS Design Space Exploration. ISCAS Anushree Mahapatra, Benjamin Carrión Schäfer
2019	A	`conf`	Partial Encryption of Behavioral IPs to Selectively Control the Design Space in High-Level Synthesis. DATE Zi Wang, Benjamin Carrión Schäfer
2019	—	`conf`	Thermal Fingerprinting of FPGA Designs through High-Level Synthesis. ACM Great Lakes Symposium on VLSI Jianqi Chen, Benjamin Carrión Schäfer
2019	J	`jnl`	Toward Self-Tunable Approximate Computing. IEEE Trans. Very Large Scale Integr. Syst. Siyuan Xu, Benjamin Carrión Schäfer
2019	J	`jnl`	VHDL vs. SystemC: Design of Highly Parameterizable Artificial Neural Networks. IEICE Trans. Inf. Syst. David Aledo, Benjamin Carrión Schäfer, Félix Moreno
2018	A*	`conf`	A machine learning based hard fault recuperation model for approximate hardware accelerators. DAC Farah Naz Taher, Joseph Callenes-Sloan, Benjamin Carrión Schäfer
2018	J	`jnl`	Accelerating cycle-accurate system-level simulations through behavioral templates. Integr. Anushree Mahapatra, Yidi Liu, Benjamin Carrión Schäfer
2018	C	`conf`	Autonomous Temperature Management through Selective Control of Exact-Approximate Tiles. ICCD Siyuan Xu, Benjamin Carrión Schäfer
2018	C	`conf`	Control Flow Checking Optimization Based on Regular Patterns Analysis. PRDC Zhiqi Zhu, Joseph Callenes-Sloan, Benjamin Carrión Schäfer
2018	C	`conf`	DEEP: Dedicated Energy-Efficient Approximation for Dynamically Reconfigurable Architectures. ICCD Siyuan Xu, Benjamin Carrión Schäfer
2018	C	`conf`	Design and Optimization of Reliable Hardware Accelerators: Leveraging the Advantages of High-Level Synthesis. IOLTS Farah Naz Taher, Mostafa Kishani, Benjamin Carrión Schäfer
2018	—	`conf`	Investigation and Optimization of Pin Multiplexing in High-Level Synthesis. ACM Great Lakes Symposium on VLSI Shuangnan Liu, Francis C. M. Lau, Benjamin Carrión Schäfer
2017	C	`conf`	Application Specific Behavioral Synthesis Design Space Exploration: Artificial Neural Networks. A Case Study. DSD Benjamin Carrión Schäfer, David Aledo, Félix Moreno
2017	C	`conf`	Approximate Reconfigurable Hardware Accelerator: Adapting the Micro-Architecture to Dynamic Workloads. ICCD Siyuan Xu, Benjamin Carrión Schäfer
2017	—	`conf`	Characterization and optimization of behavioral hardware accelerators in heterogeneous MPSoCs. ReCoSoC Yidi Liu, Monica Villaverde, Félix Moreno, Benjamin Carrión Schäfer
2017	C	`conf`	Configurable SoC In-Situ Hardware/Software Co-Design Design Space Exploration. ICCD Siyuan Xu, Benjamin Carrión Schäfer, Yidi Liu
2017	—	`conf`	Efficient behavioral intellectual properties source code obfuscation for high-level synthesis. LATS Nandeesha Veeranna, Benjamin Carrión Schäfer
2017	J	`jnl`	Enabling High-Level Synthesis Resource Sharing Design Space Exploration in FPGAs Through Automatic Internal Bitwidth Adjustments. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Benjamin Carrión Schäfer
2017	J	`jnl`	Exposing Approximate Computing Optimizations at Different Levels: From Behavioral to Gate-Level. IEEE Trans. Very Large Scale Integr. Syst. Siyuan Xu, Benjamin Carrión Schäfer
2017	—	`conf`	HW/SW co-design experimental framework using configurable SoCs. ReConFig Siyuan Xu, Jianqi Chen, Benjamin Carrión Schäfer
2017	J	`jnl`	Hardware Trojan Detection in Behavioral Intellectual Properties (IP's) Using Property Checking Techniques. IEEE Trans. Emerg. Top. Comput. Nandeesha Veeranna, Benjamin Carrión Schäfer
2017	B	`conf`	Learning-based interconnect-aware dataflow accelerator optimization. FPL Shuangnan Liu, Benjamin Carrión Schäfer
2017	J	`jnl`	Parallel High-Level Synthesis Design Space Exploration for Behavioral IPs of Exact Latencies. ACM Trans. Design Autom. Electr. Syst. Benjamin Carrión Schäfer
2017	J	`jnl`	S3CBench: Synthesizable Security SystemC Benchmarks for High-Level Synthesis. J. Hardw. Syst. Secur. Nandeesha Veeranna, Benjamin Carrión Schäfer
2017	J	`jnl`	Trust Filter: Runtime Hardware Trojan Detection in Behavioral MPSoCs. J. Hardw. Syst. Secur. Nandeesha Veeranna, Benjamin Carrión Schäfer
2017	—	`conf`	What to Lock?: Functional and Parametric Locking. ACM Great Lakes Symposium on VLSI Muhammad Yasin, Abhrajit Sengupta, Benjamin Carrión Schäfer, Yiorgos Makris, Ozgur Sinanoglu, Jeyavijayan Rajendran
2016	B	`conf`	Efficient and reliable High-Level Synthesis Design Space Explorer for FPGAs. FPL Dong Liu, Benjamin Carrión Schäfer
2016	—	`conf`	Hardware Trojan avoidance and detection for dynamically re-configurable FPGAs. FPT Nandeesha Veeranna, Benjamin Carrión Schäfer
2016	J	`jnl`	Implementation of a FPGA-Based Feature Detection and Networking System for Real-time Traffic Monitoring. CoRR Jieshi Chen, Benjamin Carrión Schäfer, Ivan Wang Hei Ho
2016	—	`conf`	On Time Redundancy of Fault Tolerant C-Based MPSoCs. ISVLSI Anjana Balachandran, Nandeesha Veeranna, Benjamin Carrión Schäfer
2016	—	`conf`	Optimization of behavioral IPs in multi-processor system-on-chips. ASP-DAC Yidi Liu, Benjamin Carrión Schäfer
2016	J	`jnl`	Probabilistic Multiknob High-Level Synthesis Design Space Exploration Acceleration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Benjamin Carrión Schäfer
2016	J	`jnl`	Source Code Error Detection in High-Level Synthesis Functional Verification. IEEE Trans. Very Large Scale Integr. Syst. Benjamin Carrión Schäfer
2016	J	`jnl`	Tunable Multiprocess Mapping on Coarse-Grain Reconfigurable Architectures With Dynamic Frequency Control. IEEE Trans. Very Large Scale Integr. Syst. Benjamin Carrión Schäfer
2015	J	`jnl`	Hierarchical High-Level Synthesis Design Space Exploration with Incremental Exploration Support. IEEE Embed. Syst. Lett. Benjamin Carrión Schäfer
2015	B	`conf`	Temperature-triggered behavioral IPs HW Trojan detection method with FPGAs. FPL Xiaotong Li, Benjamin Carrión Schäfer
2014	—	`conf`	Allocation of FPGA DSP-macros in multi-process high-level synthesis systems. ASP-DAC Benjamin Carrión Schäfer
2014	—	`conf`	HW acceleration of multiple applications on a single FPGA. FPT Yidi Liu, Benjamin Carrión Schäfer
2014	J	`jnl`	S2CBench: Synthesizable SystemC Benchmark Suite for High-Level Synthesis. IEEE Embed. Syst. Lett. Benjamin Carrión Schäfer, Anushree Mahapatra
2014	—	`conf`	Time sharing of Runtime Coarse-Grain Reconfigurable Architectures processing elements in multi-process systems. FPT Benjamin Carrión Schäfer
2012	J	`jnl`	Divide and conquer high-level synthesis design space exploration. ACM Trans. Design Autom. Electr. Syst. Benjamin Carrión Schäfer, Kazutoshi Wakabayashi
2012	J	`jnl`	Machine learning predictive modelling high-level synthesis design space exploration. IET Comput. Digit. Tech. Benjamin Carrión Schäfer, Kazutoshi Wakabayashi
2011	J	`jnl`	Precision tunable RTL macro-modelling cycle-accurate power estimation. IET Comput. Digit. Tech. Benjamin Carrión Schäfer, Kazutoshi Wakabayashi
2010	J	`jnl`	Design Space Exploration Acceleration Through Operation Clustering. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Benjamin Carrión Schäfer, Kazutoshi Wakabayashi
2010	—	`conf`	Design of complex image processing systems in ESL. ASP-DAC Benjamin Carrión Schäfer, Ashish Trambadia, Kazutoshi Wakabayashi
2010	A	`conf`	Exploiting power budgeting in thermal-aware dynamic placement for reconfigurable systems. ISLPED Shahin Golshan, Eli Bozorgzadeh, Benjamin Carrión Schäfer, Kazutoshi Wakabayashi, Houman Homayoun, Alexander V. Veidenbaum
2010	J	`jnl`	Fixed Point Data Type Modeling for High Level Synthesis. IEICE Trans. Electron. Benjamin Carrión Schäfer, Yusuke Iguchi, Wataru Takahashi, Shingo Nagatani, Kazutoshi Wakabayashi
2010	J	`jnl`	Semi-Automatic Control Unit Generation for Complex VLSI Designs. IPSJ Trans. Syst. LSI Des. Methodol. Benjamin Carrión Schäfer, Majid Sarrafzadeh
2009	J	`jnl`	Autonomous temperature control technique in VLSI circuits through logic replication. IET Comput. Digit. Tech. Benjamin Carrión Schäfer, Taewhan Kim
2008	J	`jnl`	Hotspots Elimination and Temperature Flattening in VLSI Circuits. IEEE Trans. Very Large Scale Integr. Syst. Benjamin Carrión Schäfer, Taewhan Kim
2007	B	`conf`	Temperature-Aware Compilation for VLIWProcessors. RTCSA Benjamin Carrión Schäfer, Yongho Lee, Taewhan Kim
2003	—	`—`	Acceleration of the discrete element method on a reconfigurable co-processor. Benjamin Carrión Schäfer
2002	Misc	`conf`	Analysis and Implementation of the Discrete Element Method Using a Dedicated Highly Parallel Architecture in Reconfigurable Computing. FCCM Benjamin Carrión Schäfer, Steven F. Quigley, Andrew H. C. Chan
2002	B	`conf`	Scalable Implementation of the Discrete Element Method on a Reconfigurable Computing Platform. FPL Benjamin Carrión Schäfer, Steven F. Quigley, Andrew H. C. Chan
2001	B	`conf`	Evaluation of an FPGA Implementation of the Discrete Element Method. FPL Benjamin Carrión Schäfer, Steven F. Quigley, Andrew H. C. Chan