Ben Perach

21 papers A* 2A 1C 1Journal 15Unranked 2
YearRankTypeTitle / Venue / Authors
2024 J jnl
Understanding Bulk-Bitwise Processing In-Memory Through Database Analytics.
IEEE Trans. Emerg. Top. Comput.
Ben Perach, Ronny Ronen, Benny Kimelfeld, Shahar Kvatinsky
2023 — conf
Accelerating Relational Database Analytical Processing with Bulk-Bitwise Processing-in-Memory.
NEWCAS
Ben Perach, Ronny Ronen, Shahar Kvatinsky
2023 J jnl
Accelerating Relational Database Analytical Processing with Bulk-Bitwise Processing-in-Memory.
CoRR
Ben Perach, Ronny Ronen, Shahar Kvatinsky
2023 J jnl
An Asynchronous and Low-Power True Random Number Generator using STT-MTJ.
CoRR
Ben Perach, Shahar Kvatinsky
2023 J jnl
ClaPIM: Scalable Sequence CLAssification using Processing-In-Memory.
CoRR
Marcel Khalifa, Barak Hoffer, Orian Leitersdorf, Robert Hanhan, Ben Perach, Leonid Yavits, Shahar Kvatinsky
2023 J jnl
ClaPIM: Scalable Sequence Classification Using Processing-in-Memory.
IEEE Trans. Very Large Scale Integr. Syst.
Marcel Khalifa, Barak Hoffer, Orian Leitersdorf, Robert Hanhan, Ben Perach, Leonid Yavits, Shahar Kvatinsky
2023 — conf
Enabling Relational Database Analytical Processing in Bulk-Bitwise Processing-In-Memory.
SOCC
Ben Perach, Ronny Ronen, Shahar Kvatinsky
2023 J jnl
Enabling Relational Database Analytical Processing in Bulk-Bitwise Processing-In-Memory.
CoRR
Ben Perach, Ronny Ronen, Shahar Kvatinsky
2023 A* conf
On Consistency for Bulk-Bitwise Processing-in-Memory.
HPCA
Ben Perach, Ronny Ronen, Shahar Kvatinsky
2022 J jnl
On Consistency for Bulk-Bitwise Processing-in-Memory.
CoRR
Ben Perach, Ronny Ronen, Shahar Kvatinsky
2022 J jnl
PIMDB: Understanding Bulk-Bitwise Processing In-Memory Through Database Analytics.
CoRR
Ben Perach, Ronny Ronen, Benny Kimelfeld, Shahar Kvatinsky
2022 J jnl
The Bitlet Model: A Parameterized Analytical Model to Compare PIM and CPU Systems.
ACM J. Emerg. Technol. Comput. Syst.
Ronny Ronen, Adi Eliahu, Orian Leitersdorf, Natan Peled, Kunal Korgaonkar, Anupam Chattopadhyay, Ben Perach, Shahar Kvatinsky
2021 A* conf
Efficient Error-Correcting-Code Mechanism for High-Throughput Memristive Processing-in-Memory.
DAC
Orian Leitersdorf, Ben Perach, Ronny Ronen, Shahar Kvatinsky
2021 J jnl
Efficient Error-Correcting-Code Mechanism for High-Throughput Memristive Processing-in-Memory.
CoRR
Orian Leitersdorf, Ben Perach, Ronny Ronen, Shahar Kvatinsky
2021 J jnl
The Bitlet Model: A Parameterized Analytical Model to Compare PIM and CPU Systems.
CoRR
Ronny Ronen, Adi Eliahu, Orian Leitersdorf, Natan Peled, Kunal Korgaonkar, Anupam Chattopadhyay, Ben Perach, Shahar Kvatinsky
2020 C conf
An Asynchronous and Low-Power True Random Number Generator using STT-MTJ.
ISCAS
Ben Perach, Shahar Kvatinsky
2019 J jnl
An Asynchronous and Low-Power True Random Number Generator Using STT-MTJ.
IEEE Trans. Very Large Scale Integr. Syst.
Ben Perach, Shahar Kvatinsky
2019 J jnl
CONCEPT: A Column-Oriented Memory Controller for Efficient Memory and PIM Operations in RRAM.
IEEE Micro
Nishil Talati, Heonjae Ha, Ben Perach, Ronny Ronen, Shahar Kvatinsky
2019 J jnl
MTJ-Based Hardware Synapse Design for Quantized Deep Neural Networks.
CoRR
Tzofnat Greenberg-Toledo, Ben Perach, Daniel Soudry, Shahar Kvatinsky
2019 A conf
STT-ANGIE: Asynchronous True Random Number GEnerator Using STT-MTJ.
DATE
Ben Perach, Shahar Kvatinsky
2018 J jnl
SiMT-DSP: A Massively Multithreaded DSP Architecture.
IEEE Trans. Very Large Scale Integr. Syst.
Ben Perach, Shlomo Weiss